31.5 Peripheral Dependencies
| Peripheral Name | SERCOM0 |
| Base Address | 0x4000_3000 (Peripheral Bus A) |
| NVIC IRQ Index:Source (1) | 46 : INT*[0]; 47 : INT*[1]; 48 : INT*[2]; 49 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM0_APB, Disabled, APBAMASK.SERCOM0 |
| GCLK Peripheral Channel Index:Clock Name (3) | 7 : GCLK_SERCOM0_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 12 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 4 : RX, 5 : TX |
| Peripheral Name | SERCOM1 |
| Base Address | 0x4000_3400 (Peripheral Bus A) |
| NVIC IRQ Index:Source (1) | 50 : INT*[0]; 51 : INT*[1]; 52 : INT*[2]; 53 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM1_APB, Disabled, APBAMASK.SERCOM1 |
| GCLK Peripheral Channel Index:Clock Name (3) | 8 : GCLK_SERCOM1_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 13 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 6 : RX, 7 : TX |
| Peripheral Name | SERCOM2 |
| Base Address | 0x4101_2000 (Peripheral Bus B) |
| NVIC IRQ Index:Source (1) | 54 : INT*[0]; 55 : INT*[1]; 56 : INT*[2]; 57 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM2_APB, Disabled, APBBMASK.SERCOM2 |
| GCLK Peripheral Channel Index:Clock Name (3) | 23 : GCLK_SERCOM2_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 41 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 8 : RX, 9 : TX |
| Peripheral Name | SERCOM3 |
| Base Address | 0x4101_4000 (Peripheral Bus B) |
| NVIC IRQ Index:Source (1) | 58 : INT*[0]; 59 : INT*[1]; 60 : INT*[2]; 61 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM3_APB, Disabled, APBBMASK.SERCOM3 |
| GCLK Peripheral Channel Index:Clock Name (3) | 24 : GCLK_SERCOM3_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 42 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 10 : RX, 11 : TX |
| Peripheral Name | SERCOM4 |
| Base Address | 0x4300_0000 (Peripheral Bus D) |
| NVIC IRQ Index:Source (1) | 62 : INT*[0], 63 : INT*[1], 64 : INT*[2], 65 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM4_APB, Disabled, APBDMASK.SERCOM4 |
| GCLK Peripheral Channel Index:Clock Name (3) | 34 : GCLK_SERCOM4_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 96 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 12 : RX, 13 : TX |
| Peripheral Name | SERCOM5 |
| Base Address | 0x4300_0400 (Peripheral Bus D) |
| NVIC IRQ Index:Source (1) | 66 : INT*[0], 67 : INT*[1], 68 : INT*[2], 69 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM5_APB, Disabled, APBDMASK.SERCOM5 |
| GCLK Peripheral Channel Index:Clock Name (3) | 35 : GCLK_SERCOM5_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 97 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 14 : RX, 15 : TX |
| Peripheral Name | SERCOM6 |
| Base Address | 0x4300_0800 (Peripheral Bus D) |
| NVIC IRQ Index:Source (1) | 70 : INT*[0], 71 : INT*[1], 72 : INT*[2], 73 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM6_APB, Disabled, APBDMASK.SERCOM6 |
| GCLK Peripheral Channel Index:Clock Name (3) | 36 : GCLK_SERCOM6_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 98 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 16 RX, 17 : TX |
| Peripheral Name | SERCOM7 |
| Base Address | 0x4300_0C00 (Peripheral Bus D) |
| NVIC IRQ Index:Source (1) | 74 : INT*[0], 75 : INT*[1], 76 : INT*[2], 77 : INT*[3..7] |
| MCLK APB Clock (2) | CLK_SERCOM7_APB, Disabled, APBDMASK.SERCOM7 |
| GCLK Peripheral Channel Index:Clock Name (3) | 37 : GCLK_SERCOM7_CORE |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 99 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 18 : RX, 19 : TX |
Note:
- 'INT*[n]' refers to the interrupt defined for bit n of the INTFLAG register.
- Clock Name, Default State, Mask Field.
- See GCLK.PCHCTRLm Register, where m = Index.