23.9.8 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)

Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     GP3GP2GP1GP0 
Access RRRR 
Reset 0000 
Bit 15141312111098 
 CLOCKSYNC  MASK1MASK0    
Access RRR 
Reset 000 
Bit 76543210 
  ALARM1ALARM0 CLOCKFREQCORRENABLESWRST 
Access RRRRRR 
Reset 000000 

Bits 16, 17, 18, 19 – GPn General Purpose n Synchronization Busy Status

ValueDescription
0 Write synchronization for GPn register is complete.
1 Write synchronization for GPn register is ongoing.

Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.CLOCKSYNC bit is complete.
1 Write synchronization for CTRLA.CLOCKSYNC bit is ongoing.

Bits 11, 12 – MASKn Mask n Synchronization Busy Status [n = 1..0]

ValueDescription
0 Write synchronization for MASKx register is complete.
1 Write synchronization for MASKx register is ongoing.

Bits 5, 6 – ALARMn Alarm n Synchronization Busy Status [n = 1..0]

ValueDescription
0 Write synchronization for ALARMx register is complete.
1 Write synchronization for ALARMx register is ongoing.

Bit 3 – CLOCK Clock Register Synchronization Busy Status

ValueDescription
0 Read/write synchronization for CLOCK register is complete.
1 Read/write synchronization for CLOCK register is ongoing.

Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status

ValueDescription
0 Write synchronization for FREQCORR register is complete.
1 Write synchronization for FREQCORR register is ongoing.

Bit 1 – ENABLE Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.ENABLE bit is complete.
1 Write synchronization for CTRLA.ENABLE bit is ongoing.

Bit 0 – SWRST Software Reset Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.SWRST bit is complete.
1 Write synchronization for CTRLA.SWRST bit is ongoing.