11.5.9 Cache Performance Monitoring

The Cortex M cache controller includes a programmable monitor/32-bit counter. The monitor can be configured to count the number of clock cycles, the number of data hit or the number of instruction hit.

It is important to know that the Cortex-M4 processor prefetches instructions ahead of execution. It performs only 32-bit read access on the Instruction Bus, which means:
  • One arm instruction is fetched per bus access
  • Two thumb instructions are fetched per bus access

As a consequence, two thumb instructions (e.g., NOP) need one bus access, which results in the HIT counter incrementing by 1.

Use the following sequence to activate the counter:

  • Configure the monitor counter by writing the MCFG.MODE.
    • CYCLE_COUNT is used to increment the counter along with the program counter, to count the number of cycles.
    • IHIT_COUNT is the instruction Hit counter, which increments the counter when there is a hit for the instruction in the cache.
    • DHIT_COUNT is the data Hit counter which increments the counter when there is a hit for the data in the cache.
  • Enable the counter by writing a '1' to the Cache Controller Monitor Enable bit in the Cache Monitor Enable register (MEN.MENABLE).
  • If required, reset the counter by writing a '1' to the Cache Controller Software Reset bit in the Cache Monitor Control register (MCTRL.SWRST).
  • Check the value of the monitor counter by reading the MSR.EVENT_CNT bit field.