10.1.3 Cortex-M4 Processor Features and Configuration
The following are key features and configuration of the Cortex-M4 Processor:
- Thumb® instruction set combines high code density with 32-bit performance
- IEEE 754-compliant single-precision Floating Point Unit (FPU)
- Integrated sleep modes for low power consumption
- Fast code execution permits slower processor clock or increases Sleep mode time
- Hardware division and fast digital-signal-processing orientated multiply accumulate
- Saturating arithmetic for signal processing
- Deterministic, high-performance interrupt handling for time-critical applications
- Memory Protection Unit (MPU) for safety-critical applications
- Extensive debug and trace capabilities: Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing, and code profiling.
| Features | Cortex-M4 Options | PIC32CX SG41/SG60/SG61 Configuration |
|---|---|---|
| Interrupts | 1 to 240 | 138 |
| Number of priority bits | 3 to 8 | 3 = eight levels of priority |
| Data endianness | Little-endian or big-endian | Little-endian |
| SysTick Timer calibration value | 0x80000000 | |
| MPU | Present or Not present | Present |
| Debug support level |
0 = No debug. No DAP, breakpoints, watchpoints, Flash patch, or halting debug. 1 = Minimum debug. Two breakpoints, one watchpoint, no Flash patch. 2 = Full debug minus DWT data matching. 3 = Full debug plus DWT data matching. |
3 = Full debug plus DWT data matching. |
| Trace support level |
0 = No trace. No ETM, ITM or DWT triggers and counters. 1 = Standard trace. ITM and DWT triggers and counters, but no ETM. 2 = Full trace. Standard trace plus ETM. 3 = Full trace plus HTM port. |
2 = Full trace. ITM, TPIU, ETM, and DWT triggers and counters are present. HTM port is not present |
| JTAG | Present or Not present | Not present |
| Bit Banding | Present or Not present | Not present |
| FPU | Present or Not present | Present |