36.5.3 Clocks
The peripheral is using two generic clocks and one bus clock.
The clock for the SDHC bus interface (CLK_AHB_SDHC) is enabled and disabled by the Main Clock Controller. The default state of CLK_AHB_SDHC can be found in the Peripheral Clock Masking section.
The two generic clocks are:
- The core clock GCLK_SDHCx is required to clock the SDHC core.
- The slow clock GCLK_SDHCx_SLOW is only required for certain functions. When this clock is required, GCLK_SDHCx must be enabled.