45.5 Peripheral Dependencies
| Peripheral Name | TCC0 – Timer/Counter for Control Applications 0 |
| Base Address | 0x4101_6000 (Peripheral Bus B) |
| NVIC IRQ Index:Source | 85 : CNT , DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS; 86 : MC0; 87 : MC1; 88 : MC2 89 : MC3; 90 : MC4; 91 : MC5 |
| MCLK APB Clock (1) | CLK_TCC0_APB, Disabled, APBBMASK.TCC0 |
| GCLK Peripheral Channel Index:Clock Name (2) | 25 : GCLK_TCC0, GCLK_TCC1 |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 43 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 22 : DMA Overflow/Underflow/Retrigger (OVF) 23-28 : DMA Match/Compare (MC) |
| EVSYS Users (EVSYS.USERm) (3) | 17,18 : EVx, x=0,1 (TC0 EV0..1) (A,S,R) 19-24 : Match/Compare x, x=0..5 (TCC0 MCx) (A,S,R) |
| EVSYS Generators (EVSYS.CHANNELn) | 41 : Overflow (TCC0_OVF) 42 : Trigger Event (TCC0_TRG) 43 : Counter (TCC0_CNT) 44-49 : Match/Compare x, x=0..5 (TCC0_MCx) |
| Peripheral Name | TCC1 – Timer/Counter for Control Applications 1 |
| Base Address | 0x4101_8000 (Peripheral Bus B) |
| NVIC IRQ Index:Source | 92 : CNT , DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS; 93 : MC0; 94 : MC1; 95 : MC2; 96 : MC3 |
| MCLK APB Clock (1) | CLK_TCC1_APB, Disabled, APBBMASK.TCC1 |
| GCLK Peripheral Channel Index:Clock Name (2) | 25 : GCLK_TCC0, GCLK_TCC1 |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 44 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 29 : DMA Overflow/Underflow/Retrigger (OVF) 30-33 : DMA Match/Compare (MC) |
| EVSYS Users (EVSYS.USERm) (3) | 25,26 : EVx, x=0,1 (TC1 EV0..1) (A,S,R) 27-30 : Match/Compare x, x=0..3 (TCC1 MCx) (A,S,R) |
| EVSYS Generators (EVSYS.CHANNELn) | 50 : Overflow (TCC1_OVF) 51 : Trigger Event (TCC1_TRG) 52 : Counter (TCC1_CNT) 53-56 : Match/Compare x, x=0..3 (TCC1_MCx) |
| Peripheral Name | TCC2 – Timer/Counter for Control Applications 2 |
| Base Address | 0x4200_0C00 (Peripheral Bus C) |
| NVIC IRQ Index:Source | 97: CNT, DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS; 98 : MC0 ; 99 : MC1 ; 100 : MC2 |
| MCLK APB Clock (1) | CLK_TCC2_APB, Disabled, APBCMASK.TCC2 |
| GCLK Peripheral Channel Index:Clock Name (2) | 29 : GCLK_TCC2, GCLK_TCC3 |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 67 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 34 : DMA Overflow/Underflow/Retrigger (OVF) 35-37 : DMA Match/Compare (MC) |
| EVSYS Users (EVSYS.USERm) (3) | 31,32 : EVx, x=0,1 (TC2 EV0..1) (A,S,R) 33-35 : Match/Compare x, x=0..2 (TCC2 MCx) (A,S,R) |
| EVSYS Generators (EVSYS.CHANNELn) | 57 : Overflow (TCC2_OVF) 58 : Trigger Event (TCC2_TRG) 59 : Counter (TCC2_CNT) 60-62 : Match/Compare x, x=0..2 (TCC2_MCx) |
| Peripheral Name | TCC3 – Timer/Counter for Control Applications 3 |
| Base Address | 0x4200_1000 (Peripheral Bus C) |
| NVIC IRQ Index:Source | 101 : CNT , DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS; 102 : MC0; 103 : MC1 |
| MCLK APB Clock (1) | CLK_TCC3_APB, Disabled, APBCMASK.TCC3 |
| GCLK Peripheral Channel Index:Clock Name (2) | 29 : GCLK_TCC2, GCLK_TCC3 |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 68 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 38 : DMA Overflow/Underflow/Retrigger (OVF) 39,40 : DMA Match/Compare (MC) |
| EVSYS Users (EVSYS.USERm) (3) | 36,37 : EVx, x=0,1 (TC3 EV0..1) (A,S,R) 38,39 : Match/Compare x, x=0..1 (TCC3 MCx) (A,S,R) |
| EVSYS Generators (EVSYS.CHANNELn) | 63 : Overflow (TCC3_OVF) 64 : Trigger Event (TCC3_TRG) 65 : Counter (TCC3_CNT) 66,67 : Match/Compare x, x=0,1 (TCC3_MCx) |
| Peripheral Name | TCC4 – Timer/Counter for Control Applications 4 |
| Base Address | 0x4300_1000 (Peripheral Bus D) |
| NVIC IRQ Index:Source | 104 : CNT , DFS, ERR, FAULTA, FAULTB, FAULT0, FAULT1, OVF, TRG, UFS; 105 : MC0; 106 : MC1 |
| MCLK APB Clock (1) | CLK_TCC4_APB, Disabled, APBDMASK.TCC4 |
| GCLK Peripheral Channel Index:Clock Name (2) | 38 : GCLK_TCC4 |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 100 |
| DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) | 41 : DMA Overflow/Underflow/Retrigger (OVF) 42,43 : DMA Match/Compare (MC) |
| EVSYS Users (EVSYS.USERm) (3) | 40,41 : EVx, x=0,1 (TC4 EV0..1) (A,S,R) 42,43 : Match/Compare x, x=0..1 (TCC4 MCx) (A,S,R) |
| EVSYS Generators (EVSYS.CHANNELn) | 68 : Overflow (TCC4_OVF) 69 : Trigger Event (TCC4_TRG) 70 : Counter (TCC4_CNT) 71,72 : Match/Compare x, x=0,1 (TCC4_MCx) |
Note:
- Clock Name, Default State, Mask Field.
- See GCLK.PCHCTRLm Register, where m = Index.
- (A,S,R): A = Asynchronous path, S = Synchronous path, R = Resynchronized path.