25.5.6 Sleep Mode Operation

The DMAC will continue to operate in IDLE 0 sleep mode. It does not perform transfers in IDLE 1 and IDLE 2 sleep modes, since the AHB clocks are stopped. In Standby mode, the DMAC will be internally disabled, but maintains its current configuration.

Each DMA channel can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in Channel Control A register (CHCTRLA.RUNSTDBY) must be written to '1'. The DMAC can wake up the device using interrupts from any sleep mode or perform actions through the Event System.

For channels with CHCTRLA.RUNSTDBY = 0, it is up to software to stop DMA transfers on these channels and wait for completion before going to Standby mode using the following sequence:

  1. Suspend the DMAC channels for which CHCTRLA.RUNSTDBY = 0.
  2. Check the SYNCBUSY bits of registers accessed by the DMAC channels being suspended.
  3. Go to sleep.
  4. When the device wakes up, resume the suspended channels.
Note: In Standby mode, the DMAC can only access RAM when it is not back biased (PM.STDBYCFG.BBIASxx = 0x0)
Note: In Standby mode, the DMAC can access the LP SRAM only when the power domain PD1 is not in retention and PM.STDBYCFG.BBIASLP = 0x0. The DMAC can access the SRAM in Standby mode only when the power domain PD2 is not in retention and PM.STDBYCFG.BBIASHS = 0x0.