41.4 Signal Description
The GMAC includes the following signal interfaces:
- MII, RMII to an external PHY
- MDIO interface for external PHY management
- Client APB interface for accessing GMAC registers
- Host AHB interface for memory access
- Internal GTSUCOMP signal for TSU timer count value comparison
| Signal Name | Function | MII | RMII |
|---|---|---|---|
| GTXCK | Transmit Clock or Reference Clock | TXCK | REFCK |
| GTXEN | Transmit Enable | TXEN | TXEN |
| GTX[3..0] | Transmit Data | TXD[3:0] | TXD[1:0] |
| GTXER | Transmit Coding Error | TXER | Not Used |
| GRXCK | Receive Clock | RXCK | Not Used |
| GRXDV | Receive Data Valid | RXDV | CRSDV |
| GRX[3..0] | Receive Data | RXD[3:0] | RXD[1:0] |
| GRXER | Receive Error | RXER | RXER |
| GCRS | Carrier Sense and Data Valid | CRS | Not Used |
| GCOL | Collision Detect | COL | Not Used |
| GMDC | Management Data Clock | MDC | MDC |
| GMDIO | Management Data Input/Output | MDIO | MDIO |
CAUTION: I/Os for GMAC peripheral are grouped into IO sets.
For these peripherals, it is mandatory to use I/Os that belong to the same I/O set. The timings are not guaranteed when I/Os from different I/O sets are mixed. Refer to the Pinout and Packaging chapter to get IOSET definitions.