49.5.2.1 Message Digest Example
Considering the following 512 bits message (example given in FIPS 180-4):
“61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018”
The message is written to memory in a Little Endian (LE) system architecture.
Memory Address | Address Offset / Byte Lane | |||
---|---|---|---|---|
0x3 / 31:24 | 0x2 / 23:16 | 0x1 / 15:8 | 0x0 / 7:0 | |
0x000 | 80 | 63 | 62 | 61 |
0x004–0x038 | 00 | 00 | 00 | 00 |
0x03C | 18 | 00 | 00 | 00 |
SHA1 (160 Bit Hash): The digest is stored at the memory location pointed at by the ICM_HASH pointer with a Region Offset.
Memory Address | Address Offset / Byte Lane | |||
---|---|---|---|---|
0x3 / 31:24 | 0x2 / 23:16 | 0x1 / 15:8 | 0x0 / 7:0 | |
0x000 | 36 | 3e | 99 | a9 |
0x004 | 6a | 81 | 06 | 47 |
0x008 | 71 | 25 | 3e | ba |
0x00C | 6c | c2 | 50 | 78 |
0x010 | 9d | d8 | d0 | 9c |
SHA224 (224 bit Hash):
Memory Address | Address Offset / Byte Lane | |||
---|---|---|---|---|
0x3 / 31:24 | 0x2 / 23:16 | 0x1 / 15:8 | 0x0 / 7:0 | |
0x000 | 22 | 7d | 09 | 23 |
0x004 | 22 | d8 | 05 | 34 |
0x008 | 77 | a4 | 42 | 86 |
0x00C | b3 | 55 | a2 | bd |
0x010 | e4 | bc | ad | 2a |
0x014 | f7 | b3 | a0 | bd |
0x018 | a7 | 9d | 6c | e3 |
SHA256 (256 Bit Hash):
Memory Address | Address Offset / Byte Lane | |||
---|---|---|---|---|
0x3 / 31:24 | 0x2 / 23:16 | 0x1 / 15:8 | 0x0 / 7:0 | |
0x000 | bf | 16 | 78 | ba |
0x004 | ea | cf | 01 | 8f |
0x008 | de | 40 | 41 | 41 |
0x00C | 23 | 22 | ae | 5d |
0x010 | a3 | 61 | 03 | b0 |
0x014 | 9c | 7a | 17 | 96 |
0x018 | 61 | ff | 10 | b4 |
0x01C | ad | 15 | 00 | f2 |
Considering the following 1024 bits message (example given in FIPS 180-4):
“6162638000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000018”
The message is written to memory in a Little Endian (LE) system architecture.
Memory Address | Address Offset / Byte Lane | |||
---|---|---|---|---|
0x3 / 31:24 | 0x2 / 23:16 | 0x1 / 15:8 | 0x0 / 7:0 | |
0x000 | 80 | 63 | 62 | 61 |
0x004–0x078 | 00 | 00 | 00 | 00 |
0x07C | 18 | 00 | 00 | 00 |