51.5 Peripheral Dependencies

Peripheral Name ADC0 – Analog-to-Digital Converter 0
Base Address 0x4300_1C00 (Peripheral Bus D)
NVIC IRQ Index:Source 118 : OVERRUN, WINMON; 119 : RESRDY
MCLK APB Clock (1) CLK_ADC0_APB, Disabled, APBDMASK.ADC0
GCLK Peripheral Channel Index:Clock Name (2) 40 : GCLK_ADC0
PAC Peripheral Peripheral Identifier (PAC.WRCTRL) 103
DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) 68 : RESRDY, 69 : SEQ
EVSYS Users (EVSYS.USERm) (3) 55 : Start Conversion (ADC0 START) (A,S,R) 56 : Flush ADC0 (ADC0 SYNC) (A,S,R)
EVSYS Generators (EVSYS.CHANNELn) 103 : Result Ready (ADC0_RESRDY) 104 : Window Monitor (ADC0_WINMON)
Peripheral Name ADC1 – Analog-to-Digital Converter 1
Base Address 0x4300_2000 (Peripheral Bus D)
NVIC IRQ Index:Source 120 : OVERRUN, WINMON; 121 : RESRDY
MCLK APB Clock (1) CLK_ADC1_APB, Disabled, APBDMASK.ADC1
GCLK Peripheral Channel Index:Clock Name (2) 41 : GCLK_ADC1
PAC Peripheral Peripheral Identifier (PAC.WRCTRL) 104
DMA Trigger Index:Source (DMAC.CHCTRLAk,k=0,1,...31) 70 : RESRDY, 71 : SEQ
EVSYS Users (EVSYS.USERm) (3) 57 : Start Conversion (ADC1 START) (A,S,R) 58 : Flush ADC1 (ADC1 SYNC) (A,S,R)
EVSYS Generators (EVSYS.CHANNELn) 105 : Result Ready (ADC1_RESRDY) 106 : Window Monitor (ADC1_WINMON)
Note:
  1. Clock Name, Default State, Mask Field.
  2. See GCLK.PCHCTRLm Register, where m = Index.
  3. (A,S,R): A = Asynchronous path, S = Synchronous path, R = Resynchronized path.