39.6.3.1 Without DMAC

  1. Write the Interrupt Enable and Interrupt Disable Registers (IER and IDR) in order to configure the PCC interrupt mask.
  2. Write the Mode Register (MR) fields ISIZE, SCALE, DSIZE, ALWYS, HALFS and FRSTS in order to configure the PCC. Do not enable the PCC in this write access.
  3. Write the PCC Enable bit in the Mode Register (MR.PCEN) to '1' in order to enable the PCC. Do not change the configuration from the previous step.
  4. Wait for a Data Ready, either by polling the Data Ready flag in the Interrupt Status Register (ISR.DRDY) or by waiting for the corresponding interrupt.
  5. Check the Overrun Error flag (ISR.OVRE).
  6. Read the data in the Reception Holding Register (RHR).
  7. If new data are expected, go to step 4.
  8. Disable the PCC by writing MR.PCEN to '0' without changing the configuration.