36.7.21 Normal Interrupt Signal Enable Register
| Name: | NISIER |
| Offset: | 0x38 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BOOTAR | CINT | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CREM | CINS | BRDRDY | BWRRDY | DMAINT | BLKGE | TRFC | CMDC | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 14 – BOOTAR Boot Acknowledge Received Signal Enable
Note: This register entry is specific to the e.MMC operation mode.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.BOOTAR is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.BOOTAR is set. |
Bit 8 – CINT Card Interrupt Signal Enable
Note: This register entry is specific to the SD/SDIO operation mode.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.CINT is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.CINT is set. |
Bit 7 – CREM Card Removal Signal Enable
Note: This register entry is specific to the SD/SDIO operation mode.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.CREM is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.CREM is set. |
Bit 6 – CINS Card Insertion Signal Enable
Note: This register entry is specific to the SD/SDIO operation mode.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.CINS is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.CINS is set. |
Bit 5 – BRDRDY Buffer Read Ready Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.BRDRDY is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.BRDRDY is set. |
Bit 4 – BWRRDY Buffer Write Ready Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.BWRRDY is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.BWRRDY is set. |
Bit 3 – DMAINT DMA Interrupt Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.DMAINT is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.DMAINT is set. |
Bit 2 – BLKGE Block Gap Event Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.BLKGE is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.BLKGE is set. |
Bit 1 – TRFC Transfer Complete Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.TRFC is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.TRFC is set. |
Bit 0 – CMDC Command Complete Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when NISTR.CMDC is set. |
| 1 | ENABLED | An interrupt is generated when NISTR.CMDC is set. |