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Advanced Security and Features Set MCU PIC32CX SG41/SG60/SG61 Family Data Sheet
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27
Non-Volatile Memory Controller (NVMCTRL)
27.5
Functional Description
27.5.8
SmartEEPROM
PIC32CX SG41/SG60/SG61 Family Data Sheet
1-MB Flash, 256-KB SRAM with optional Hardware Security Module, Crypto, 1 MSPS 12-bit ADC, QSPI, USB, Ethernet, and PTC
1
Configuration Summary
2
Ordering Information
3
Block Diagram
4
Pinout and Packaging
5
Signal Descriptions List
6
Power Supplies
7
Device Start-Up
8
Product Mapping
9
Memories
10
Processor and Architecture
11
Cortex-M Cache Controller (CMCC)
12
Peripheral Access Controller (PAC)
13
Device Service Unit (DSU)
14
Clock System
15
Generic Clock Controller (GCLK)
16
Main Clock (MCLK)
17
32.768 kHz Oscillators Controller (OSC32KCTRL)
18
Oscillators Controller (OSCCTRL)
19
Supply Controller (SUPC)
20
Power Manager (PM)
21
Reset Controller (RSTC)
22
Watchdog Timer (WDT)
23
Real-Time Counter (RTC)
24
Frequency Meter (FREQM)
25
Direct Memory Access Controller (DMAC)
26
External Interrupt Controller (EIC)
27
Non-Volatile Memory Controller (NVMCTRL)
27.1
Overview
27.2
Features
27.3
Block Diagram
27.4
Peripheral Dependencies
27.5
Functional Description
27.5.1
Principle of Operation
27.5.2
Memory Organization
27.5.3
Memory Bank Swapping
27.5.4
AHBMUX Arbitration
27.5.5
Region Lock Bits
27.5.6
Command and Data Interface
27.5.7
Safe Flash Update Using Dual Banks
27.5.8
SmartEEPROM
27.5.8.1
Principle of Operation
27.5.8.2
Address Spaces
27.5.8.3
Data Structures
27.5.8.4
SmartEEPROM Virtual Size
27.5.8.5
SmartEEPROM Wear Leveling
27.5.8.6
Writing and Reading the SmartEEPROM
27.5.8.7
SmartEEPROM Sector Reallocation
27.5.9
NVM User Configuration
27.5.10
Security Bit
27.5.11
Line Cache
27.5.12
Error Correction Code
27.5.13
Reset During Operation
27.5.14
Chip Erase
27.5.15
Chip Erase Hard Lock
27.5.16
Boot Protect Hard Lock
27.5.17
Boot Read Protection
27.5.18
Immutable Boot, Boot Read Protection, and Secure Debug Features Overview
27.6
Register Summary
28
RAM Error Correction Code (RAMECC)
29
I/O Pin Controller (PORT)
30
Event System (EVSYS)
31
Serial Communication Interface (SERCOM)
32
SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
33
SERCOM Serial Peripheral Interface (SERCOM SPI)
34
SERCOM Inter-Integrated Circuit (SERCOM I
2
C)
35
Quad Serial Peripheral Interface (QSPI)
36
SD/MMC Host Controller (SDHC)
37
Inter-IC Sound Controller (I
2
S)
38
Control Area Network (CAN)
39
Parallel Capture Controller (PCC)
40
Universal Serial Bus (USB)
41
Ethernet MAC (GMAC)
42
Position Decoder (PDEC)
43
Configurable Custom Logic (CCL)
44
Timer/Counter (TC)
45
Timer/Counter for Control Applications (TCC)
46
Advanced Encryption Standard (AES)
47
Public Key Cryptography Controller (PUKCC)
48
True Random Number Generator (TRNG)
49
Integrity Check Monitor (ICM)
50
Hardware Security Module (HSM)
51
Analog-to-Digital Converter (ADC)
52
Analog Comparators (AC)
53
Digital-to-Analog Converter (DAC)
54
Peripheral Touch Controller (PTC)
55
Electrical Specifications 85°C
56
Electrical Specifications 125°C
57
Packaging Information
58
Schematic Checklist
59
Conventions
60
Acronyms and Abbreviations
61
PIC32CX SG41/SG60/SG61 Revision History
Microchip Information
27.5.8 SmartEEPROM
