3.2.1 System Initialization Overview

The following figure illustrates the system initialization flow, consisting of hardware and firmware initialization, after power-on.
Figure 3-4. System Initialization

After connecting the supply voltage to the VS pin, the ATA8210/15 always starts in OFFMode. All internal circuits are disconnected from the power supply. See OFFMode from Related Links. The user can wake-up the ATA8210/15 by one of the following Power-on Reset (POR) events:

  • Setting the PWRON pin to HIGH
  • Setting one of the NPWRON (1-6) pins to LOW

A POR enables the DVCC regulator. The FRC oscillator starts when the DVCC voltage reaches the operating voltage. At the same time, trigger the internal AVR reset. After reaching stable operating conditions, the FRC provides the clock for the hardware initialization state machine. The initialization state machine reads the fuses and resets the SRAM content to 0x00. The internal AVR reset is released when the hardware initialization is done. The system is now controlled by the firmware.

The firmware steps through the following tasks:

  • Check for a correct wake-up condition by reading the pin registers (PINB and PINC) to identify the wake-up source.
    • Correct wake-up source – The wake-up source is signaled as an event.
    • No wake-up source – The wake-up is considered invalid and the ATA8210/15 switches back to OFFMode.
    There is no checking for reset sources like watchdog reset, external reset or Brown-out Reset (BOR). This implies that the chip goes to OFFMode if, for example, a watchdog reset occurred and no (N) PWRON pin was triggered.
  • Disable the watchdog timer.
  • Firmware initialization – The system is initialized according to the EEPROM settings. See Firmware Initialization from Related Links.

After successful firmware initialization, the system enters the selected operating mode after the system start; otherwise, the firmware disables the watchdog timer, sets the SYS_ERR flag and stays in an endless loop. In this scenario, the SPI communication is still possible, such as to program the EEPROM or read out the error code from the SRAM. See Error Codes from Related Links.

The operating mode after the system start is selectable by the EEPROM variable eepTrxConfig.sysStartConfig.OPM[1:0]:

  • IDLEMode
  • RXMode
  • PollingMode

In the variables eepTrxConfig.sysStartConfig and eepTrxConfig.sysStartSvcChConfig, the user can configure various options, which are addressed during the Start-up operating mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0019 sysStartConfig RF_CAL — VCO_TUNE IDLEModeSelector — TMDEN OPM[1:0]
0x001A sysStartSvcChConfig enaPathB enaPathA Ch[1:0] — Ser[2:0]

The following table provides details about options that are relevant for each operating mode.

Table 3-1. Operating Mode Options
OPM RF_CALVCO_TUNEIDLEMode SelectorTMDENenaPathBenaPathACh[1:0]Ser[2:0]
IDLEMode — — x — — — — —
RxMode x x x x x x x x
PollingMode — x x x — — — x(1)
Note:
  1. If PollingMode is selected, bits 0 to 3 of eepTrxConfig.sysStartSvcChConfig define the start index of the polling array.

For more details on the description of the various operating modes, see Operating Modes Overview from Related Links. See sEEPromTrxConfig eepTrxConf from Related Links.