5.2 Application Board Design

This section describes the application and reference board design for the ATA8210/15 and gives recommendations about optimizing the layout for the ATA8210/15 application.

The following figure shows the schematic of the ATA8210/15 application board. The application boards are delivered using the SPDT RF switch; no SAW is used and no antenna tuning is applied. The Ant1 pin of the application board is the 50Ω RF input and output. The following tables summarize the corresponding board populations for 315 MHz, 433.92 MHz and 868 MHz, respectively. See Bill of Material of the Application Board for 315 MHz, 3V Application, Bill of Material of the Application Board for 433.92 MHz, 3V Application and Bill of Material of the Application Board for 868.3 MHz, 3V Application in the Application Board Design from Related Links. The boards are manufactured using FR4 material with a PCB thickness of 1 mm.

The application board also provides the option of verifying the performance of RFIN_LB(HB) directly without using the SPDT. The electrical characteristics are primarily measured using a matching network between either RFIN_LB or RFIN_HB and Ant2 or a matching network between SPDT_ANT and Ant1. This is shown for each parameter in the description of the electrical characteristics in the ATA8210/ATA8215 UHF ASK/FSK Receiver Data Sheet (9344E). For example, a (1) means that the sensitivity is measured directly at pin 1 RFIN_LB. Add the insertion loss of the SPDT, if used.

For more details on the matching networks of the receive path without using the SPDT, see LNA and Mixer from Related Links. For more details on the matching networks for using the SPDT RF switch, see SPDT RF Switch from Related Links.

All matching networks are also available for the 915 MHz application in the sections referred to.

The layout of the application board is illustrated in the following figure.

For the layout illustrated in the preceding figure, the component diagram shows in the following figure.

The following items must be considered while designing a layout for the ATA8210/15 application board:

1. The decoupling capacitor of AVCC, C₁₂ must be placed as close as possible to pin 12 because, otherwise, the series inductance is too high and supply bypassing is no longer effective at high frequencies.
2. The decoupling capacitor of DVCC, C₁₄ must be placed as close as possible to pin 20. This decoupling capacitor must be connected directly to the DGND pin and ground layer. See Layout of the ATA8210/15 Application Board in the Application Board Design from Related Links. Otherwise, the sensitivity of the receiver can be worsened by the spurious clock emission of the integrated AVR.
3. The decoupling capacitor of VS, C₁₃ must be placed as close as possible to pin 13 because, otherwise, the series inductance is too high and supply bypassing is no longer effective at high frequencies.
4. Direct connection of the DGND pin to the exposed die pad must be avoided, and at least four vias must be placed under the exposed die pad. If this is not done, the isolation of the integrated AVR from the RF front end is worse. The exposed die pad is also the RF ground for receive operation and reduced sensitivity results from bad ground connection on the exposed die pad.
5. The crystal must be placed as close as possible to the IC to avoid extra capacitance on XTAL1 and XTAL2.
6. It is advisable to design the lines carrying the RF signal to be as short as possible and place the elements of the matching networks as close as possible to the IC (Ant1 to SPDT_ANT and SPDT_RX to RFIN_LB/RFIN_HB).
7. Avoid routing XTAL, AVCC and VS lines in parallel and close to each other over long distances; doing so reduces the coupling of the XTO signals to the supply voltage. Failing to do so can cause spurious receiver emissions.
8. Avoid routing XTAL1 and XTAL2 lines in parallel and close to each other over long distances, to avoid a reduction of the XTO oscillation margin.
9. If using only one RFIN pin, it is advisable for the other RFIN to be connected to GND.
10. If the SPDT is not used, it is advisable to leave pins 3, 4 and 6 open.

The following tables show the bill of material of the application boards for 315 MHz, 433.92 MHz and 868.3 MHz applications. The required power supply for the application board is 3V. Components not mentioned in the following tables are not mounted.