4.1 Overview

The ATA8210/15 consists of an analog front-end, digital signal processing blocks (DSP), an 8-bit AVR sub-system and various supply modules such as oscillators and power regulators (see the following hardware block diagram of the ATA8210/15).

Together with the fractional-N PLL, the Crystal Oscillator (XTO) generates the Local Oscillator (LO) signal for the mixer in RXMode. The RF signal comes either from the Low-band Input (RFIN_LB) or from the High-band Input (RFIN_HB) and is amplified by the Low Noise Amplifier (LNA) and down-converted by the mixer to the Intermediate Frequency (IF) using the LO signal. To achieve enhanced system sensitivity without affecting blocking performance, use a 10 dB IF amplifier with low-pass filter characteristic.

After the mixer, the IF signal is sampled using a high-resolution Analog-to-Digital Converter (ADC).

Within the RX Digital Signal Processing (RX DSP), the received signal from the ADC is filtered by a digital channel filter and demodulated. Two data receive paths, path A and path B, are included in the RX DSP after the digital channel filter. In addition, configure the receive path to provide the digital output of an internal temperature sensor (Temp(ϑ)).

The AVR CPU with 24 KB firmware ROM and 20 KB user Flash controls the system for the ATA8210. The 1024-byte EEPROM, 1024-byte SRAM and other peripherals are supporting the receiver handling. Two GPIO ports, PB[7:0] and PC[5:0], are available for external digital connections; for example, as an alternate function, connect the SPI interface to PORTB. The EEPROM configuration and SPI commands control the ATA8210/15, and the firmware in the ROM mainly determines the functional behavior. The EEPROM settings can modify much of the configuration. The firmware running on the AVR gives access to the hardware functionality of the ATA8210/15. Extensions to this firmware can be added in the 20 KB of Flash memory for the ATA8210. The RX DSP registers are addressed directly and accessible from the AVR. A set of sequencer state machines is included to perform RX path operations (such as enable, disable and receive) which require a defined timing parallel to the AVR program execution.

The power management contains Low-dropout (LDO) regulators and Reset circuits for the supply voltages VS, AVCC and DVCC of the ATA8210/15. In OFFMode, all the supply voltages AVCC and DVCC are switched OFF to achieve very low current consumption. The ATA8210/15 can be powered up by activating the PWRON pin or one of the NPWRON[6:1] pins because they are still active in OFFMode. The AVCC domain can be switched ON and OFF independently from DVCC. The ATA8210/15 includes two idle modes. In IDLEMode(RC), only the DVCC voltage regulator, the FRC and SRC oscillators are active, and the AVR uses a power-down mode to achieve low current consumption. Use the same power-down mode during the inactive phases of the PollingMode. In IDLEMode(XTO), the AVCC voltage domain as well as the XTO are additionally activated.

An integrated watchdog timer is available to restart the ATA8210/15 when it is not served within the configured time-out period.