Introduction
(Ask a Question)The PolarFire® FPGA family includes multiple embedded low-power and performance-optimized transceivers. Each transceiver has Physical Medium Attachment (PMA) and Physical Coding Sub-layer (PCS) logics, and interfaces to the FPGA fabric.
The transceiver has a multi-lane architecture with each lane natively supporting serial data transmission rates from 250 Mbps to 12.7 Gbps.
This document describes how to perform the dynamic reconfiguration of Clock Conditioning Circuit (CCC) and transceivers in a PolarFire FPGA by changing the output clock frequency in a glitch-free way.
Important: The SmartDebug and APB DRI accesses must not be
initiated at the same time.
Important: The DRI protocol standard uses “Master” and “Slave.” The
equivalent Microchip terminology used in this document is
Initiator and Target,
respectively.