2.3 AC Parameters

Figure 2-1. AC Timing Diagram

Table 2-2. AC Parameters⁽³⁾
Parameter	Symbol	Direction	Min.	Typ.	Max.	Unit	Notes
Wake Low Duration⁽⁴⁾	t_WLO	To ATSHA206A	60	—	—	µs	Minimum time to guarantee wake under all conditions.
Wake High Delay to Data Comm.	t_WHI	To ATSHA206A	2.5	—	—	ms	SIO should be stable and > V_SIO for this entire duration.
High-Side Glitch Filter at Active⁽²⁾	t_{HIGNORE_IO}	To ATSHA206A	45	—	—	ns	Pulses shorter than this in width will be ignored by the device when in Active mode.
Low-Side Glitch Filter at Active⁽²⁾	t_{LIGNORE_IO}	To ATSHA206A	45	—	—	ns	Pulses shorter than this in width will be ignored by the device when in Active mode.
High-Side Glitch Filter at Sleep	t_{HIGNORE_S}	To ATSHA206A	15	—	—	µs	Pulses shorter than this in width will be ignored by the device when in Sleep mode.
Low-Side Glitch Filter at Sleep	t_{LIGNORE_S}	To ATSHA206A	15	—	—	µs	Pulses shorter than this in width will be ignored by the device when in Sleep mode.
Watchdog Reset⁽¹⁾	t_WATCHDOG	To ATSHA206A	0.7	1.3	1.7	s	Maximum time from wake until the device is forced into Sleep mode.

Note:

These parameters are ensured through characterization but not tested in production.
“Active” refers to either I/O mode or Compute mode, as opposed to Sleep mode.
V_SIO means the high level to which SIO is driven during the I/O mode. The driver could be either the totem pole driver on the MCU or the resistor when the ATSHA206A returns data.
When the device is in Sleep mode, pulses ≤t_WLO but ≥ t_{LIGNORE_S} may cause the device to wake up and transition to the I/O mode. When in the I/O mode, the device is designed to ensure that no legal t_START or t_ZLO low pulse will cause the device to reset.

Figure 2-2. AC Data Transfer Timing Diagram

Table 2-3. AC Data Transfer ParametersApplicable from T_A = −5°C to +85°C, V_SIO = +2.0V to +4.2V, C_L = 100 pF⁽²⁾ (unless otherwise noted).
Parameter	Symbol	Direction	Min.	Typ.	Max.	Unit	Notes
Start Pulse Duration	t_START	To ATSHA206A	4.10	4.34	4.56	µs	Note 1
Start Pulse Duration	t_START	From ATSHA206A	4.60	6.00	8.60	µs	Note 1
Zero Transmission High Pulse	t_ZHI	To ATSHA206A	4.10	4.34	4.56	µs	Note 1
Zero Transmission High Pulse	t_ZHI	From ATSHA206A	4.60	6.00	8.60	µs	Note 1
Zero Transmission Low Pulse	t_ZLO	To ATSHA206A	4.10	4.34	4.56	µs	Note 1
Zero Transmission Low Pulse	t_ZLO	From ATSHA206A	4.60	6.00	8.60	µs	Note 1
Bit Time	t_BIT	To ATSHA206A	37	39	—	µs	Note 1
Bit Time	t_BIT	From ATSHA206A	41	54	78	µs	Note 1
Turnaround Delay	t_TURNAROUND	From ATSHA206A	64	80	131	µs	The ATSHA206A initiates the first low-going transition after this time interval following the start of the last bit (t_BIT) of the Transmit flag.
Turnaround Delay	t_TURNAROUND	To ATSHA206A	93	—	—	µs	After the ATSHA206A transmits the last bit of a block, the system must wait this interval before sending the first bit of a flag.

Note:

t_START, t_ZLO, t_ZHI, and t_BIT are designed to be compatible with a standard UART running at 230.4 Kbaud for both transmit and receive. The UART should be set to seven data bits, no parity, and one Stop bit.
All performance parameters assume C_L ≤ 100 pF. Bus capacitance exceeding 100 pF will reduce performance, both of AC and DC parameters.

ATSHA206A