1.3.2 Speed Limitations

Due to the high-speed nature of I3C transactions, the MIPI I3C Specification provides different ways for target devices on the bus to notify the controller of any delays in the user application. This can be done by setting the BCR0 bit in the I3CxBCR register. After the controller reads the I3CxBCR register during the Dynamic Address Assignment process, the controller can then read the I3CxMWS and I3CxMRS registers using the Get Maximum Data Speed (GETMXDS) CCC.

The Target can notify the controller of the following speed limitations:
  1. Clock-to-Data Turnaround Time (TSCO): It is the time duration between reception of an SCL edge by the Target and the start of driving an SDA change. Refer to the device data sheet for exact TSCO measurements. The user can notify the controller of this value through the I3CxMRS register.
  2. Maximum Read Turnaround Time (MRT): Occasionally, it may happen that the controller requests specific data from the Target, and the application requires extra time to prepare the data before it can be read back by the controller. In such cases, the user can specify a maximum read turnaround time using the I3CxMRT register. When a non-zero value is specified in the I3CxMRT register, the MRS[6] bit in the I3CxMRS register can be used to notify the controller whether a Stop can be inserted between the request for data (by “writing” read index) and actual read of the data.
  3. Maximum Write/Read Speed (MWS/MRS): While the I3C module can support transactions up to the maximum bus frequency of 12.5 MHz, the application may be slow to respond. In such cases the Target can notify the controller of the maximum write and read speeds using the I3CxMWS and I3CxMRS registers respectively.