18.4.1 PMD Control Register 0
Note:
- Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals; however, peripherals clocked by FOSC/4 are not affected.
| Name: | PMD0 |
| Offset: | 0x062 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYSCMD | FVRMD | HLVDMD | CRCMD | SCANMD | NVMMD | CLKRMD | IOCMD | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SYSCMD Disable Peripheral System Clock Network(1)
| Value | Description |
|---|---|
| 1 | System clock network disabled (FOSC) |
| 0 | System clock network enabled |
Bit 6 – FVRMD Disable Fixed Voltage Reference
| Value | Description |
|---|---|
| 1 | FVR module disabled |
| 0 | FVR module enabled |
Bit 5 – HLVDMD Disable High/Low-Voltage Detect
| Value | Description |
|---|---|
| 1 | HLVD module disabled |
| 0 | HLVD module enabled |
Bit 4 – CRCMD Disable CRC Module
| Value | Description |
|---|---|
| 1 | CRC module disabled |
| 0 | CRC module enabled |
Bit 3 – SCANMD Disable NVM Memory Scanner
| Value | Description |
|---|---|
| 1 | NVM memory scanner module disabled |
| 0 | NVM memory scanner module enabled |
Bit 2 – NVMMD Disable NVM access
| Value | Description |
|---|---|
| 1 |
All memory reading and writing is disabled; NVMCON registers cannot be written |
| 0 |
All memory reading and writing is enabled |
Bit 1 – CLKRMD Disable Clock Reference
| Value | Description |
|---|---|
| 1 | Clock reference module disabled |
| 0 | Clock reference module enabled |
Bit 0 – IOCMD Disable Interrupt-on-Change
| Value | Description |
|---|---|
| 1 | Interrupt-on-change module is disabled |
| 0 | Interrupt-on-change module is enabled |