18.4.5 PMD Control Register 4
| Name: | PMD4 |
| Offset: | 0x066 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMA3MD | DMA2MD | DMA1MD | CLC4MD | CLC3MD | CLC2MD | CLC1MD | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 5, 6, 7 – DMAnMD Disable DMAn
| Value | Description |
|---|---|
| 1 | DMAn module disabled |
| 0 | DMAn module enabled |
Bits 1, 2, 3, 4 – CLCnMD Disable CLCn
| Value | Description |
|---|---|
| 1 | CLCn module disabled |
| 0 | CLCn module enabled |