10 Peripherals Configuration Summary

Table 10-1. Peripherals Configuration Summary for PIC32CM MC00
Peripheral Base Address IRQ AHB

CLK

 APB

CLK

 Generic

CLK

 PAC Events DMA Sleep

Walking

Enabled

at reset

 Enabled

at reset

 Index Index Prot at

reset

 User Generator Index
AHB-APB-Bridge A 0x40000000 - Y - - - - - - - N/A
PAC 0x40000000 0 Y Y - 0 N - 81:ACCERR - N/A
PM 0x40000400 0 - Y - 1 N - - - N/A
MCLK 0x40000800 0 - Y - 2 N - - - Y
RSTC 0x40000C00 - - Y - 3 N - - - N/A
OSCCTRL 0x40001000 0 - Y 0:FDPLL96M clk source 4 N - 1:XOSC_FAIL - Y
1:FDPLL96M 32kHz
OSC32KCTRL 0x40001400 0 - Y - 5 N - 2:XOSC32K_FAIL - Y
SUPC 0x40001800 0 - Y - 6 N - - - N/A
GCLK 0x40001C00 - - Y - 7 N - - - N/A
WDT 0x40002000 1 - Y - 8 N - - - Y
RTC 0x40002400 2 - Y - 9 N - 3: CMP0/ALARM0 - Y
4: CMP1
5: OVF
6:13: PER0-7
EIC 0x40002800 3, NMI - Y 2 10 N - 14-29:EXTINT0-15 - Y
FREQM 0x40002C00 4 - Y 3: Measure 11 N - - - N/A
4: Reference
TSENS 0x40003000 5 - N 5: TSENS 12 N 0: START 30: WINMON 1: RESRDY N/A
AHB-APB-Bridge B 0x41000000 - Y - - - - - - - N/A
PORT 0x41000000 - Y - 0 N 1-4: EV0-3 - - Y
DSU 0x41002000 - Y Y - 1 Y - - - N/A
NVMCTRL 0x41004000 6 Y Y - 2 N - - - Y
DMAC 0x41006000 7 Y N/A - 3 N 5-8: CH0-3 31-34: CH0-3 - Y
MTB 0x41008000 - - N/A - 4 N 42: START - - N/A
43: STOP
AHB-APB-Bridge C 0x42000000 - Y - - - - - - - N/A
EVSYS 0x42000000 8 - N 6-17: one per Channel 0 N - - - Y
SERCOM0 0x42000400 9 - N 19: CORE 1 N - - 2: RX Y
18: SLOW 3: TX
SERCOM1 0x42000800 10 - N 20: CORE 2 N - - 4: RX Y
18: SLOW 5: TX
SERCOM2 0x42000C00 11 - N 21: CORE 3 N - - 6: RX Y
18: SLOW 7: TX
SERCOM3 0x42001000 12 - N 22: CORE 4 N - - 8: RX Y
18: SLOW 9: TX
Reserved 0x42001400 - - - - - - - - - -
TCC0 0x42002400 13 - N 23 9 N 9-10: EV0-1 35: OVF 10: OVF Y
36: TRG
11-14: MC0-3 37: CNT 11-14: MC0-3
38-41: MC0-3
TCC1 0x42002800 14 - N 23 10 N 15-16: EV0-1 42: OVF 15: OVF Y
43: TRG
17-18: MC0-1 44: CNT 16-17: MC0-1
45-46: MC0-1
TCC2 0x42002C00 15 - N 24 11 N 19-20: EV0-1 47: OVF 18: OVF Y
48: TRG
21-22: MC0-1 49: CNT 19-20: MC0-1
50-51: MC0-1
TC0 0x42003000 16 - N 25 12 N 23: EVU 52: OVF 21: OVF Y
53-54: MC0-1 22-23: MC0-1
TC1 0x42003400 17 - N 25 13 N 24: EVU 55: OVF 24: OVF Y
56-57: MC0-1 25-26: MC0-1
TC2 0x42003800 18 - N 26 14 N 25: EVU 58: OVF 27: OVF Y
59-60: MC0-1 28-29: MC0-1
TC3 0x42003C00 19 - N 26 15 N 26: EVU 61: OVF 30: OVF Y
62-63: MC0-1 31-32: MC0-1
TC4 0x42004000 20 - N 27 16 N 27: EVU 64: OVF 33: OVF Y
65-66: MC0-1 34-35: MC0-1
ADC0 0x42004400 21 - N 28 17 N 28: START 67: RESRDY 36: RESRDY Y
29: FLUSH 68: WINMON
ADC1 0x42004800 22 - N 29 18 N 30: START 69: RESRDY 37: RESRDY Y
31: FLUSH 70: WINMON
SDADC 0x42004C00 25 - N 30 19 N 32: START 71: RESRDY 38: RESRDY Y
33: FLUSH 72: WINMON
AC 0x42005000 23 - N 33 20 N 34-35: SOC0-1 73-74: COMP0-1 - Y
75: WIN0
DAC 0x42005400 24 - N 31 21 N 36: START 76: EMPTY 39: EMPTY Y
Reserved 0x42005800 - - - - - - - - - -
CCL 0x42005C00 - - N 32 23 N 37-40: LUTIN0-3 77-80: LUTOUT0-3 - Y
Reserved 0x42006000 - - - - - - - - - -
PDEC 0x42006800 26 - N 34 26 N 44: EVU0 83: OVF - Y
84: ERR
45: EVU1 85: DIR
86: VLC
46: EVU2 87: MC0
88: MC1
DIVAS 0x48000000 - Y - - - - - - - N/A

Registers can be 8, 16, or 32 bits wide. Atomic 8-bit, 16-bit, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.

PAC Write-Protection Register Property:

Some registers are optionally write-protected by the Peripheral Access Controller (PAC).

PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For more details, refer to the PAC - Peripheral Access Controller.

Read-Synchronized, Write-Synchronized Register Property:

Some registers or bit fields within a register require synchronization when read and/or written.

Synchronization is denoted by the "Read-Synchronized" ("Read-Synchronized Bits”) and "Write-Synchronized" ("Write-Synchronized Bits”) property in each individual register description. For more details, refer to Register Synchronization.

Enable-Protected Register Property:

Some registers or bit fields within a register can only be written when the peripheral is disabled.

Such protection is denoted by the "Enable-Protected" ("Enable-Protected Bits") property in each individual register description.