48 Revision History

Revision E - August 2023

The following updates were added in this revision of the document.


Section	Updates
5-Volt, 128-KB Flash, 16-KB SRAM with Advanced Analog	Added Software and Tools Support features.
11.1 Clock Distribution	Updated Figure 11-1.
14 Oscillators Controller (OSCCTRL)	Updated Figure 14-2. Added note in XOSCFAIL Bit in STATUS Register.
15 32.768 kHz Oscillators Controller (OSC32KCTRL)	Added the fifth paragraph in 15.6.4 32.768 kHz Internal Oscillator (OSC32K) Operation.
17 Supply Controller (SUPC)	Added paragraph in BODVDDRDY Bit in STATUS Register.
23 Real-Time Counter (RTC)	Updated Property field and added notes in COUNT and COUNT Registers.
24 Direct Memory Access Controller (DMAC)	Changed (BEATSIZE + 1) by (BEATSIZE) in 24.5.2.7 Addressing.
25 External Interrupt Controller (EIC)	Updated 25.2 Features.
26 Nonvolatile Memory Controller (NVMCTRL)	Updated the table of PSZ Bits in PARAM Register.
27 I/O Pin Controller (PORT)	Added note in 27.6.4 Events.
28 Event System (EVSYS)	Added first column in Table 28-1.
30 SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)	Updated second paragraph in 30.6.2.5 Data Transmission. Added note in 30.6.3.5 LIN Host. Added note in 30.6.3.10 Sample Adjustment. Added note in HDRDLY and BRKLEN Bits in CTRLC Register.
31 SERCOM Serial Peripheral Interface (SERCOM SPI)	Updated first paragraph in 31.6.3.5 Hardware Controlled SS. Added note in MSSEN Bit in CTRLB Register.
32 SERCOM Inter-Integrated Circuit (SERCOM I²C)	Added info of DRDY Bit in INTFLAG Register.
33 Timer Counter (TC)	Updated notes in 33.6.2.8 Capture Operations. Updated first paragraph in 33.6.2.8.1 Event Capture Action on Events or I/Os. Updated Figure 33-13 and updated third paragraph and note in 33.6.2.8.2 Period and Pulse-Width (PPW) Capture Action on Events. Updated Figure 33-14. Updated Figure 33-15. Updated Property field and updated note 1 in COUNT Register. Updated Property field in CCx Register. Updated Property field and updated note 1 in COUNT Register. Updated Property field and updated note 1 in COUNT Register.
34 Timer/Counter for Control (TCC) Applications	Updated Property field and added note in CPTENx, DMAOS, MSYNC, PRESCYNC, RUNSTDBY, PRESCALER, RESOLUTION, ENABLE and SWRST Bits in CTRLA Register. Updated Property field and added note in STATUS Register. Updated Property field and added note in COUNT Register. Added note in PATT Register. Updated Property field, updated info of SWAPx, POLx and CICCENx Bits and added note in SWAPx, POLx, CICCENx, CIPEREN, RAMP and WAVEGEN Bits in WAVE Register. Added note in PER Register. Updated Name, Offset and Property fields and added note in CCx Register. Updated Property field, added note and updated info in PGVBx and PGEBx Bits in PATTBUF Register. Updated Property field, added note and updated info in PERBUF and DITHERBUF Bits in PERBUF Register. Updated Name, Offset and Property fields, added note and updated info in DITHERBUF Bit in CCBUFx Register.
36 Analog-to-Digital Converter (ADC)	Removed an erroneous reference to DAC in 36.2 Features, Figure 36-1 and Figure 36-8. Updated second paragraph in 36.6.2.3 Operation. Updated 36.6.2.8 Conversion Timing and Sampling Rate with new information after Figure 36-6.
38 Analog Comparators (AC)	Added note in 38.6.10 Offset Compensation.
39 Digital-to-Analog Converter (DAC)	Updated second paragraph in 39.6.1 Principle of Operation. Updated second bullet in 39.6.4 Interrupts.
43 Electrical Characteristics 85℃	Updated info of VREFA and deleted info of VREFB in Table 43-1. Updated P_INT and PI/O in Table 43-3. Updated Typ. and Max. Values in Table 43-8. Updated Figure 43-3. Moved PAI_53 to Modules/Peripherals Active Currents <= 550 µA in Table 43-9. Added FCLK_6a and FCLK_6b in Table 43-13. Added note 3 in Table 43-19. Deleted info of ADC_63 inTable 43-25. Updated Figure 43-6, updated MSP_1 in Table 43-31 and updated SSP_1 in Table 43-32. Updated Min. and Max. Values in Table 43-34 and Table 43-35.
44 Electrical Characteristics 125°C	Updated P_INT and PI/O in Table 44-2. Added 44.17 Serial Peripheral Interface (SERCOM SPI) Mode Electrical Specifications. Updated Typ. and Max. Values in Table 44-6. Added Active Current info of 1.5µA, 2µA, 75µA, 100µA, 200µA and 250µA in Table 44-7.
46 Schematic Checklist	Added second paragraph in 46.1 Introduction. Added second paragraph in 46.2 Operation in Noisy Environment. Added note in 46.5 External Reset Circuit. Added note in 46.8.1 Cortex Debug Connector (10-pin). Added note in 46.8.2 20-pin IDC JTAG Connector.

Revision D - June 2021

Terminology used in this document may not match with the contents of other Microchip documentation and collateral. For any questions or concerns regarding terminology, contact a Microchip support or sales representative.

This revision contains numerous typographical updates throughout the document. All other updates are listed in the following table:


Section	Updates
5-Volt, 128-KB Flash, 16-KB SRAM with Advanced Analog	Addition of AEC-Q100 Grade qualifications
Configuration Summary	Removed a redundant table
Ordering Information	Added a note for AEC-Q100 Qualification
PDEC	Updated the equation for Filtering in Input Selection and Filtering Added SYNBUSY.STATUS verbiage to the STATUS register for the following bit fields: HERR WINERR MPERR IDXERR QERR
Electrical Specifications at 85℃	Updated the Conditions column for the last two rows of the table in I/O Pin Electrical Specifications Removed the Minimum Specification for XOSC_35 in External Crystal Oscillator and Clock (XOSC) Electrical Specifications Removed the Min. and Max. Specifications for XOSC32_19 in External 32 kHz Crystal Oscillator (XOSC32K) Electrical Specifications Updated the Min. and Max. Specifications for OSC48M_1 in Internal 48 MHz RC Oscillator (OSC48M) Removed a Redundant table from Fractional Digital Phase Locked Loop (FDPLL96M) Updated the Min., Max and Units Specifications for SDAC_23 and SDAC_25 in Digital-to-Analog Converter (DAC) Electrical Specifications Added a note to Temperature Sensor (TSENS) Electrical Specifications
Electrical Specifications at 125℃	Updated the Min. and Max. Specifications for OSC48M_1 in the table in Internal 48 MHz RC Oscillator (OSC48M) Updated the Min., Max. and Units specifications for SDAC_23 and SDAC_25 in DAC Module Electrical Specifications

Revision C - April 2021

This revision contains numerous typographical updates throughout the document. All other updates are listed in the following table:


Section	Updates
General	Throughout the entire document all references of “Master” were changed to “Host,” and “Slave” was changed to “Client,” where applicable.
Electrical Specifications at 85℃	Updated the Absolute Maximum Ratings table with new specifications for VDD and VDDIO Updated Power Supply table with new specifications for REG_4, REG_5, REG_9, REG_11, REG_38, and REG_39 Updated the CPU Active Power table with the addition of APWR_5 and APWR_7 Updated the note of the CPU Idle Power table Updated Peripheral Active Current with a new table Updated the table in the I/O Pin Electrical Specifications with new max value for DI_21, and new data for Note 1, Note 2, and Note 4 Updated VR_27 min and max values in Internal Voltage Reference Specifications Updated the notes in External Crystal Oscillator and Clock (XOSC) Electrical Specifications Update the notes in External 32kHz Crystal Oscillator (XOSC32K) Electrical Specifications Updated Internal 32.768 kHz RC Oscillator (OSC32K) with new min and max values for OSC32K_3b Updated the min and max values for OSC48M_1 in Internal 48MHz RC Oscillator (OSC48M) Removed erroneous reference to PPM<100 from the “Fractional Digital Phase Locked Loop (FDPLL96M) Electrical Specifications” table in Fractional Digital Phase Locked Loop (FDPLL96M) Updated the min and max specifications for SADC_31a, SADC_31b, SADC_31c, SADC_31d, SADC_37a, SADC_37b, SADC_37c, SADC_37d, DADC+31a, DADC_31b, DADC_31c, DADC_31d, DADC_37a, DADC_37b, DADC_37c, and DADC_37d in Analog to Digital Converter (ADC) Electrical Specifications Updated the Min. and max. specifications for DSDADC_31 and DSDADC_37 in Sigma-Delta Analog to Digital Converter (SDADC) Electrical Specifications Updated the minimum specifications in the table for Frequency Meter (FREQM) Electrical Specifications Updated the minimum specifications in the table for Position Decoder (PDEC) Electrical Specifications
Electrical Specifications at 125℃	New section.
Appendix A: Migration	New section.

Revision B - November 2020

This revision contains numerous typographical updates throughout the document. All other updates are listed in the following table:


Section	Updates
Pinout	Updated the 32-pin VQFN diagrams with proper pin numbering. Updated Note 1 in the Pinout table. Updated the 48-pin VQFN diagrams with proper pin numbering. Updated Note 1 in the Pinout table.
General	For each chapter the topic “Product Dependencies” was renamed to “Peripheral Dependencies” and the content was condensed into a table.
Power Supply and Start-Up Considerations	Removed redundant images from Typical Powering Schematics and added a cross reference to the proper schematics.
Processor and Architecture	New verbiage was added to the SysTick section of Cortex-M0+ Peripherals.
Product Mapping	Updated the diagram with a new section for PORT, DIVAS, and Reserved off the IOBUS section.
NVM User Row Mapping	Updated the BODCORE calibration with a new Production Setting.
Clock System	Updated the Diagram in On-Demand, Clock Requests changing CLKEN to CHEN.
GCLK	Added new information about the Peripheral channel to the second line item in Initialization.
OSCCTRL	Added new verbiage regarding the XOSC Register to External Multipurpose Crystal Oscillator (XOSC) Operation Added new Verbiage to the Clock Failure detection section of Clock Failure Detection Operation Added new verbiage for OSC48M Operation at the end of 48 MHz Internal Oscillator (OSC48M) Operation New verbiage for configuration was added to Loop Divider Ratio Rates The following register was updated with new verbiage to notes and/or bitfields: OSC48MDIV
OSC32KCTRL	Updated 32.768 kHz External Crystal Oscillator (XOSC32K) Operation with new verbiage regarding disabling the XOSC32K bit Updated Clock Failure Detection Operation with new verbiage at the end of the Clock Failure Detection Section
SUPC	Added content for the SDADC to the SEL bitfield of the VREF register
DSU	Updated the REVISION bit of the DID Register with new text for device revision.
PM	Updated verbiage for the SysTick Overflow Interrupt in SRAM Automatic Low-Power Mode.
PAC	Removed erroneous text from the Interrupts section Added new notes to the PERID bit of the WRCTRL Register Removed the TSENS bit from the INTFLAGA and STATUSA Registers
RTC	Added verbiage for STANDBY Sleep Mode to Sleep Mode Operation Updated the following registers with new verbiage for the bitfield COUNT: COUNT32 COUNT16 Added a new note to the CLOCK register
EIC	Updated Asynchronous Edge detection Mode with new verbiage for asynchronous edge detection.
NVMCTRL	Updated Command and Data Interface with verbiage for confirming INTFLAG.READY is ‘1’.
PORT	Updated PORT Access Priority with new verbiage about IOBUS writes.
EVSYS	Added new verbiage to Event System Channel for the busy bit Updated Channel Path with new verbiage regarding 2.5 GCLK_EVSYS periods Added new verbiage to The Overrun Channel n Interrupt regarding the GCLK Added new verbiage to Software Event for channels with a resynchronized path Updated the User Multiplexer Number table in the USERm Register
SERCOM USART	Updated Collision Detection with verbiage for the Peripheral Bus (APB) Updated Interrupts with new verbiage for the Data Register Empty interrupt Updated Sleep Mode Operation with new verbiage for the FERR, PERR, and STANDBY power consumption Removed erroneous DBGCTRL register Updated the following registers with new FERR and PERR information: INTENSET INTFLAG
SERCOM SPI	Updated Preloading of the Client Shift Register to avoid the Preload function Updated Interrupts with new verbiage for the Data Register Empty interrupt Updated the following registers with new verbiage: CTRLB DBGCTRL
SERCOM I²C	Updated 10-Bit Addressing to show it is not available in Client mode Updated Quick Command with new verbiage for the Quick Command mode Updated Client DMA with new verbiage for transaction length of data Updated Interrupts with new verbiage for the DRDY, AMATCH, PREC, SB, and MB interrupts Updated the STATUS Register with new verbiage for the SEXTOUT, CLKHOLD, LOWTOUT, COLL, and BUSERR bits Removed the TENBITEN bit from the ADDR Register and updated the ADDRMASK and ADDR bits with new bit lengths
TC	Updated Double Buffering with new verbiage for the STATUS Register Updated Sleep Mode Operation with information about STANDBY Sleep mode Updated the following 8 bit registers with new verbiage: STATUS DBGCTRL Updated the following 16 bit registers with new verbiage: STATUS DBGCTRL SYNCBUSY Updated the following 32 bit registers with new verbiage: STATUS DBGCTRL
TCC	Updated the Configuration Summary to display a 16-bit Counter Size for TCC#1 Updated Double Buffering with new verbiage for clearing the STATUS bits twice Updated Dithering Operation with verbiage regarding avoiding an external retrigger event Updated RAMP2 Operation in Ramp Operation with verbiage for supporting counting up mode Added new verbiage to the Counter Re-trigger sections of Events detailing the non-support of dithering or if RAMP2 operation is used with a prescaler Added new verbiage to Sleep Mode Operation detailing STANDBY Sleep mode Updated the following registers: CTRLA - Removed the ALOCK bit CTRLBCLR - new verbiage to the IDXCMD bit DBGCTRL - new verbiage for the DBGRUN bit EVCTRL - Updated the EVACT1 and EVACT0 bit descriptions STATUS - Removed the WAVEBUFV bit and added new text to the register description
CCL	Updated Initialization with text for disabling Updated Enabling, Disabling and Resetting with new verbiage about the PAC being enabled Updated SEQCTRL with new verbiage in the note Updated LUTCTRLn with new verbiage in the note
ADC	Updated Offset and Gain Correction with new verbiage to not use it for 8 and 10-bit conversion resolution Updated Reference Buffer Compensation Offset with new information regarding discarding conversions of the ADC Removed the DAC from the Diagram in Host/Client Operation Updated Sleep Mode Operation with new information for STANDBY Sleep mode Updated the following registers: REFCTRL - New verbiage for discarding ADC conversions INPUTCTRL - Removal of DAC reference from the MUXPOS bit OFFSETCORR - Updated text for not using Offset correction for 8-bit and 10-bit conversion resolution DBGCTRL - New verbiage for DBGRUN bit
SDADC	Updated Features to display 2 external analog differential pairs Added a new paragraph for STANDBY Sleep Mode to Sleep Mode Operation Updated the following registers: REFCTRL - new values in the table for REFSEL DBGCTRL - Updated verbiage for the DBGRUN bit
AC	Updated the DBGCTRL register with new verbiage for the DBGRUN bit.
DAC	Updated Sleep Mode Operation with new verbiage for STANDBY Updated the INTFLAG register with new verbiage for the EMPTY bit Updated the DBGCTRL Register with new verbiage for the DBGRUN bit
TSENS	Updated Overview and Features to remove erroneous wording Updated the CTRLB register with a new register property and note Updated the DBGCTRL register with new verbiage for the DBGRUN bit
FREQM	Updated the CTRLB Register with a new note.
PDEC	Updated Prescaler Selection to remove erroneous text In Position and Rotation Measurement all references starting with Q, such as Q4, Q4S, etc were changed to read X4, and X4S etc Removed the Count Event Action topic Removed The description for “Count” from the bulleted item list in Events Updates were done to the following registers: EVCTRL - Updated verbiage for the EVE, EVEI, EVINV, and EVACT1 bits
Electrical Characteristics	Updates to formatting, notes, min, typ and max specs were made to the tables and content of the following topics: Operating Frequencies and Thermal Limitations Power Supply CPU Active Power CPU Idle Power CPU Standby Power Peripheral Active Current Wake-up Timing I/O Pin Electrical Specifications Internal Voltage Reference Specifications Maximum Clock Frequencies Electrical Specifications XOSC Electrical Specifications XOSC32K Electrical Specifications Internal 32.768 kHz RC Oscillator (OSC32K) Internal 48MHz RC Oscillator (OSC48M) Ultra Low Power internal 32kHz RC Oscillator (OSCULP32K) Frequency Digital Phase Locked Loop (FDPLL96M) Digital-to-Analog Converter (DAC) Module ADC Electrical Specifications SDADC Electrical Specifications Temperature Sensor (TSENS) Electrical Specifications Analog Comparator (AC) Electrical Specifications SERCOM SPIx Mode Electrical Specifications SERCOM USART Electrical Specifications SERCOM I²C Electrical Specifications TC Input Module Electrical Specifications TCC Module Electrical Specifications FREQM Electrical Specifications Flash NVM Electrical Specifications Position Decoder (PDEC) Electrical Specifications
Packaging	Removed the Packaging table for moisture sensitivity from the following packages: 48-pin TQFP 48-pin VQFN 32-pin TQFP Added in packaging tables for the following package: 32-pin VQFN Updated the Package Marking Information, and removed the Thermal Considerations topics.
Schematic Checklist	Modified the following schematics: Single Power Supply Schematic Dual Power Supply Schematic Modified the External Analog Reference Connections table and associated notes Added notes to the schematics in External Reset Circuit and removed a redundant table Replaced the text in Unused or Unconnected Pins Modified the External Clock Source Connections table Updated the schematics and table in Crystal Oscillator Added in two new topics: External Slow Clock Source 32.768 kHz Crystal Oscillator Replaced the opening text in Programming and Debug Ports

Revision A - July 2020

This is the initial released version of this document.