Pin Allocation Tables

Table . 14-Pin Allocation Table
I/O14-Pin

PDIP

SOIC

TSSOP

ADCC (12-bit Differential)10-bit DACOperational Amplifier

Comparator

ZCD

TimersNCO16-Bit

PWM/

CCP

CWGCLCI2C/SPIEUARTIOCInterruptBasic
RA013

ANA0(5)

DACOUT1OPA1IN3+

OPA1IN3-

OPA1(1)

C1IN0+SS2(1)IOCA0ICSPDAT

ICDDAT

RA112

ANA1(5)

ADCREF+

DAC1REF0+

DAC2REF0+

C1IN0-

CLP1IN0-

IOCA1ICSPCLK

ICDCLK

RA211

ANA2(5)

ADCREF-

DAC2REF0-

DAC1REF0-

DACOUT2

OPA1IN2+

OPA1IN2-

ZCD1T0CKI(1)CWG1(1)IOCA2INT(1)
RA34IOCA3MCLR

VPP

RA43

ANA4(5)

T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA52

ANA5(5)

T1CKI(1)

T2IN(1)

PWM1ERS(1)CLCIN3(1)IOCA5

CLKIN

OSC1

SOSCI

RC010

ANC0(5)

OPA1IN0+CLP1IN0+SCL1(1,3,4)

SCK1(1,3,4)

CK2(1,3)IOCC0
RC19

ANC1(5)

OPA1IN0-

C1IN1-

CLP1IN1-

T4IN(1)

PWM2ERS(1)CLCIN2(1)SDA1(1,3,4)

SDI1(1,3,4)

RX2(1)

DT2(1,3)

IOCC1
RC28ANC2(5)

ADACT(1)

OPA1OUT

C1IN2-

CLP1IN2-

IOCC2
RC37

ANC3(5)

OPA1IN1+

OPA1IN1-

C1IN3-

CLP1IN3-

PWMIN1(1)

CCP2(1)

CLCIN0(1)SS1(1)IOCC3
RC46

ANC4(5)

T3G(1)CLCIN1(1)

SCL2(1,3,4)

SCK2(1,3,4)

CK1(1,3)

IOCC4
RC55

ANC5(5)

T3CKI(1)PWMIN0(1)

CCP1(1)

SDA2(1,3,4)

SDI2(1,3,4)

RX1(1)

DT1(1,3)

IOCC5
VDD1VDD
VSS14VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMPLP1

TMR0NCO1PWM11

PWM12

PWM21

PWM22

CCP1

CCP2

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

CLKR
Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. This pin can be used as either a positive or negative analog input channel to the ADC.
Table . 20-Pin Allocation Table
I/O20-Pin

PDIP

SOIC

SSOP

20-Pin

QFN

ADCC (12-bit Differential)10-bit DACOperational AmplifierComparatorZCDTimersNCO16-Bit

PWM/

CCP

CWGCLCI2C/SPIEUSARTIOCInterruptBasic
RA01916

ANA0(5)

DACOUT1OPA1IN3+

OPA1IN3-

OPA1(1)

C1IN0+IOCA0ICSPDAT

ICDDAT

RA11815

ANA1(5)

VREF+(ADC)

DAC1REF0+

DAC2REF0+

C1IN0-

CLP1IN0-

SS2(1)

IOCA1ICSPCLK

ICDCLK

RA21714

ANA2(5)

VREF-(ADC)

DAC1REF0-

DAC2REF0-

DACOUT2

OPA1IN2+

OPA1IN2-

ZCD1T0CKI(1)CWG1(1)CLCIN0(1)IOCA2INT(1)
RA341IOCA3MCLR

VPP

RA4320

ANA4(5)

T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA5219

ANA5(5)

T1CKI(1)

T2IN(1)

PWM1ERS(1)IOCA5

CLKIN

OSC1

SOSCI

RB41310

ANB4(5)

OPA1IN0-

CLCIN2(1)SDA1(1,3,4)

SDI1(1,3,4)

IOCB4
RB5129

ANB5(5)

OPA1IN0+CLCIN3(1)

SDA2(1,3,4)

SDI2(1,3,4)

RX1(1)

DT1(1,3)

IOCB5
RB6118

ANB6(5)

SCL1(1,3,4)

SCK1(1,3,4)

IOCB6
RB7107ANB7(5)

SCL2(1,3,4)

SCK2(1,3,4)

CK1(1,3)IOCB7
RC01613ANC0(5)C2IN0+CK2(1,3)IOCC0
RC11512ANC1(5)C1IN1-

CLP1IN1-

T4IN(1)PWM2ERS(1)RX2(1)

DT2(1,3)

IOCC1
RC21411ANC2(5)

ADACT(1)

OPA1OUTC1IN2-

CLP1IN2-

IOCC2
RC374ANC3(5)

OPA1IN1+

OPA1IN1-

C1IN3-

CLP1IN3-

PWMIN1(1)

CCP2(1)

CLCIN1(1)IOCC3
RC463ANC4(5)T3G(1)IOCC4
RC552ANC5(5)T3CKI(1)PWMIN0(1)

CCP1(1)

IOCC5
RC685ANC6(5)SS1(1)IOCC6
RC796ANC7(5)IOCC7
VDD118VDD
VSS2017VSS
OUT(2)ADGRDA

ADGRDB

CMP1

CMPLP1

TMR0NCO1PWM11

PWM12

PWM21

PWM22

CCP1

CCP2

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

CLKR
Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. This pin can be used as either a positive or negative analog input channel to the ADC.
Table . 28-Pin Allocation Table
I/O28-Pin

SPDIP

SSOP

28-Pin

VQFN

ADCC (12-bit Differential)10-bit DACOperational AmplifierComparatorZCDTimersNCO16-Bit

PWM/

CCP

CWGCLCI2C/SPIEUSARTIOCInterruptBasic
RA0227ANA0OPA1(1)C1IN0-

CLP1IN0-

CLCIN0(1)IOCA0
RA1328ANA1(5)

OPA1OUT

OPA2IN1+

OPA2IN1-

C1IN1-

CLP1IN1-

CLCIN1(1)IOCA1
RA241ANA2

VREF- (ADC)

DAC1REF0-

DACOUT1

OPA1IN0+

OPA1IN0-

C1IN0+

CLP1IN0+

IOCA2
RA352ANA3(5)

VREF+ (ADC)

DAC1REF0+

C1IN1+IOCA3
RA463ANA4OPA1IN1+

OPA1IN1-

T0CKI(1)IOCA4
RA574ANA5(5)OPA1IN2+

OPA1IN2-

SS1(1)IOCA5
RA6107ANA6(5)IOCA6CLKOUT

OSC2

RA796ANA7IOCA7CLKIN

OSC1

RB02118ANB0(5)DAC2REF0+CLP1IN1+ZCD1CWG1(1)

SS2(1)

IOCB0INT(1)
RB12219ANB1

OPA2OUT

OPA1IN3+

OPA1IN3-

C1IN3-

CLP1IN3-

SCL2(1,3,4)

SCK2(1,3,4)

IOCB1
RB22320ANB2(5)

OPA2IN3+

OPA2IN3-

SDA2(1,3,4)

SDI2(1,3,4)

IOCB2
RB32421ANB3

OPA2IN2+

OPA2IN2-

C1IN2-

CLP1IN2-

IOCB3
RB42522ANB4(5)

ADACT(1)

OPA2IN0+

OPA2IN0-

IOCB4
RB52623ANB5

DAC2REF0-

T1G(1)IOCB5
RB62724ANB6(5)CLCIN2(1)CK2(1,3)IOCB6ICSPCLK

ICDCLK

RB72825ANB7DACOUT2

OPA2IN4-(6)

T6IN(1)CLCIN3(1)RX2(1)

DT2(1,3)

IOCB7ICSPDAT

ICDDAT

RC0118ANC0T1CKI(1)

T3CKI(1)

T3G(1)

IOCC0SOSCO
RC1129ANC1(5)PWMIN1(1)

CCP2(1)

IOCC1SOSCI
RC21310ANC2PWMIN0(1)

CCP1(1)

IOCC2
RC31411ANC3(5)T2IN(1)PWM1ERS(1)SCL1(1,3,4)

SCK1(1,3,4)

IOCC3
RC41512ANC4SDA1(1,3,4)

SDI1(1,3,4)

IOCC4
RC51613ANC5

OPA3IN0+

T4IN(1)PWM2ERS(1)IOCC5
RC61714ANC6(5)OPA3OUTCK1(1,3)IOCC6
RC71815ANC7RX1(1)

DT1(1,3)

IOCC7
RE3126IOCE3MCLR

VPP

VDD2017VDD
VSS8

19

5

16

VSS
OUT(2)ADGRDA

ADGRDB

CMP1

CMPLP1

TMR0NCO1PWM11

PWM12

PWM21

PWM22

CCP1

CCP2

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

CLKR
Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. This pin can be used as either a positive or negative analog input channel to the ADC.
  6. This input is only for Operational Amplifier resistor ladder.
Table . 40/44-Pin Allocation Table
I/O40-Pin

PDIP

40-Pin

QFN

44-Pin

TQFP

ADCC (12-bit Differential)10-bit DACOperational AmplifierComparatorZCDTimersNCO16-Bit

PWM/

CCP

CWGCLCI2C/SPIEUSARTIOCInterruptBasic
RA021719ANA0OPA1(1)C1IN0-

CLP1IN0-

CLCIN0(1)IOCA0
RA131820ANA1(5)

OPA1OUT

OPA2IN1+

OPA2IN1-

C1IN1-

CLP1IN1-

CLCIN1(1)IOCA1
RA241921ANA2

VREF- (ADC)

DAC1REF0-

DACOUT1

OPA1IN0+

OPA1IN0-

C1IN0+

CLP1IN0+

IOCA2
RA352022ANA3(5)

VREF+ (ADC)

DAC1REF0+

C1IN1+IOCA3
RA462123ANA4OPA1IN1+

OPA1IN1-

T0CKI(1)IOCA4
RA572224ANA5(5)OPA1IN2+

OPA1IN2-

SS1(1)IOCA5
RA6142931ANA6(5)IOCA6CLKOUT

OSC2

RA7132830ANA7IOCA7CLKIN

OSC1

RB03388ANB0(5)DAC2REF0+CLP1IN1+ZCD1CWG1(1)

SS2(1)

IOCB0INT(1)
RB13499ANB1

OPA2OUT

OPA1IN3+

OPA1IN3-

C1IN3-

CLP1IN3-

SCL2(1,3,4)

SCK2(1,3,4)

IOCB1
RB2351010ANB2(5)

OPA2IN3+

OPA3IN3-

SDA2(1,3,4)

SDI2(1,3,4)

IOCB2
RB3361111ANB3

OPA2IN2+

OPA2IN2-

C1IN2-

CLP1IN2-

IOCB3
RB4371214ANB4(5)

ADACT(1)

OPA2IN0+

OPA2IN0-

IOCB4
RB5381315ANB5DAC2REF0-T1G(1)IOCB5
RB6391416ANB6(5)CLCIN2(1)CK2(1,3)IOCB6ICSPCLK

ICDCLK

RB7401517ANB7DACOUT2

OPA2IN4-(6)

T6IN(1)CLCIN3(1)RX2(1)

DT2(1,3)

IOCB7ICSPDAT

ICDDAT

RC0153032ANC0T1CKI(1)

T3CKI(1)

T3G(1)

IOCC0SOSCO
RC1163135ANC1(5)PWMIN1(1)

CCP2(1)

IOCC1SOSCI
RC2173236ANC2PWMIN0(1)

CCP1(1)

IOCC2
RC3183337ANC3(5)T2IN(1)PWM1ERS(1)SCL1(1,3,4)

SCK1(1,3,4)

IOCC3
RC4233842ANC4SDA1(1,3,4)

SDI1(1,3,4)

IOCC4
RC5243943ANC5

OPA3IN0+

T4IN(1)PWM2ERS(1)IOCC5
RC6254044ANC6(5)

OPA3OUT

OPA4IN1+

OPA4IN1-

CK1(1,3)IOCC6
RC72611ANC7

OPA3IN0-

RX1(1)

DT1(1,3)

IOCC7
RD0193438AND0OPA4IN0+
RD1203539AND1OPA4OUT
RD2213640AND2(5)

OPA4IN0-

RD3223741AND3(5)
RD42722AND4
RD52833AND5(5)
RD62944AND6
RD73055AND7(5)
RE082325ANE0
RE192426ANE1(5)
RE2102527ANE2
RE311618IOCE3MCLR

VPP

VDD11

32

7

26

7

28

VDD
VSS12

31

6

27

6

29

VSS
OUT(2)ADGRDA

ADGRDB

CMP1

CMPLP1

TMR0NCO1PWM11

PWM12

PWM21

PWM22

CCP1

CCP2

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

CLKR
Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. This pin can be used as either a positive or negative analog input channel to the ADC.
  6. This input is only for Operational Amplifier resistor ladder.