2.1 High-speed PWM

In the AVR®, the timer/counters can be used to generate PWM signals. PWM base frequency is determined by timer clock frequency and top counter value. Faster clock frequency will increase the PWM base frequency and vice versa. Lower top value will reduce the time for overflow, which thereby increases the PWM frequency. The PWM base frequency can be calculated as follows:

PWM Frequency = Timer clock speed / Timer resolution

ATtiny26 devices features the high-speed PWM, which allows the user to run the timer at a higher speed than the CPU clock. Timer/Counter1 supports two accurate, high speed, 8-bit Pulse Width Modulators using clock speeds up to 64MHz. It has two clocking modes; synchronous mode and asynchronous mode. The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. Asynchronous mode can be enabled by setting the PCKE bit from the PLLCSR Register (PLLCSR > PCKE = 1). Timer/Counter1 features a prescaler setting, which provides clock selections between PCK to PCK/16384 in asynchronous mode. Setting the PSR1 bit in TCCR1B Register resets the prescaler. The block diagram of Timer/Counter1 Prescaler is shown in the following diagram:
Figure 2-1. Timer/Counter1 Prescaler
Note: Refer the device datasheet for more details on configuration and usage of internal RC Oscillator and PLL.

The PLL of Timer/Counter1 needs a 1MHz reference clock. We can use the internal RC oscillator to generate 1MHz by configuring the OSCCAL register. This clock output will be used as reference to PLL which can generate a recommended maximum frequency of 64MHz. Hence, the maximum PWM frequency that could be generated with best resolution is given as follows:

PWM Frequency = 64MHz / 256 = 250kHz

Increasing the base frequency beyond this will be at the expense of reduced resolution, since fewer steps are available from 0% to 100% duty cycle. Altering the value of the Output Compare Registers (OCR) changes the duty cycle. Increasing the OCR value increases the duty cycle. The PWM output is high until the OCR value is reached, and low until the timer reaches the top value and wraps back to 0. This is shown in following figure.
Figure 2-2. Counter Values and PWM Output
With 64MHz timer clock and a top value 3, PWM base frequency of 16MHz can be achieved. However, the OCR value is now limited to 0, 1 (25% duty cycle), 2 (50% duty cycle), or 3 (100% duty cycle). This shows that lowering the top value can increase the PWM base frequency, but reduces the resolution.
To achieve the maximum output frequency from the timer, it must be run in non-PWM mode. Both the OCR value and the top value must be set to 0. The counter is then stuck at 0. Setting the Output Compare Match action to ‘toggle output’ makes the timer toggle the output on every timer clock tick. The result is a 32MHz signal, as shown in following figures.
Figure 2-3.  High Frequency Digital Output