25.5.2 Reinforced Safety Watchdog Timer Mode Register
Note: The first write access prevents any further modification of the value of this
register; read accesses remain possible. The WDV value must not be modified within
three slow clock periods following a restart of the watchdog performed by means of a
write access in the RSWDT_CR, else the watchdog may trigger an end of period earlier
than expected.
| Name: | RSWDT_MR |
| Offset: | 0x04 |
| Reset: | 0x3FFFAFFF |
| Property: | Read/Write Once |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WDIDLEHLT | WDDBGHLT | ALLONES[11:8] | |||||||
| Access | |||||||||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ALLONES[7:0] | |||||||||
| Access | |||||||||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WDDIS | WDRSTEN | WDFIEN | WDV[11:8] | ||||||
| Access | |||||||||
| Reset | 1 | 1 | 0 | 1 | 1 | 1 | 1 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WDV[7:0] | |||||||||
| Access | |||||||||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 29 – WDIDLEHLT Watchdog Idle Halt
| Value | Description |
|---|---|
| 0 | The RSWDT runs when the system is in idle mode. |
| 1 | The RSWDT stops when the system is in idle state. |
Bit 28 – WDDBGHLT Watchdog Debug Halt
| Value | Description |
|---|---|
| 0 | The RSWDT runs when the processor is in debug state. |
| 1 | The RSWDT stops when the processor is in debug state. |
Bits 27:16 – ALLONES[11:0] Must Always Be Written with 0xFFF
Bit 15 – WDDIS Watchdog Disable
| Value | Description |
|---|---|
| 0 | Enables the RSWDT. |
| 1 | Disables the RSWDT. |
Bit 13 – WDRSTEN Watchdog Reset Enable
| Value | Description |
|---|---|
| 0 | A Watchdog fault (underflow or error) has no effect on the resets. |
| 1 | A Watchdog fault (underflow or error) triggers a watchdog reset. |
Bit 12 – WDFIEN Watchdog Fault Interrupt Enable
| Value | Description |
|---|---|
| 0 | A Watchdog fault (underflow or error) has no effect on interrupt. |
| 1 | A Watchdog fault (underflow or error) asserts interrupt. |
Bits 11:0 – WDV[11:0] Watchdog Counter Value
Defines the value loaded in the 12-bit watchdog counter.