50.2 Embedded Characteristics

  • 4 Channels
  • Common Clock Generator Providing Thirteen Different Clocks
    • A Modulo n Counter Providing Eleven Clocks
    • Two Independent Linear Dividers Working on Modulo n Counter Outputs
  • Independent Channels
    • Independent 16-bit Counter for Each Channel
    • Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or Non-Overlapping Time) for Each Channel
    • Independent Push-Pull Mode for Each Channel
    • Independent Enable Disable Command for Each Channel
    • Independent Clock Selection for Each Channel
    • Independent Period, Duty-Cycle and Dead-Time for Each Channel
    • Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel
    • Independent Programmable Selection of The Output Waveform Polarity for Each Channel, with Double Buffering
    • Independent Programmable Center- or Left-aligned Output Waveform for Each Channel
    • Independent Output Override for Each Channel
    • Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration
    • Independent Update Time Selection of Double Buffering Registers (Polarity, Duty Cycle) for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration
  • External Trigger Input Management (e.g., for DC/DC or Lighting Control)
    • External PWM Reset Mode
    • External PWM Start Mode
    • Cycle-By-Cycle Duty Cycle Mode
    • Leading-Edge Blanking
  • 2 2-bit Gray Up/Down Channels for Stepper Motor Control
  • Spread Spectrum Counter to Allow a Constantly Varying Duty Cycle (only for Channel 0)
  • Synchronous Channel Mode
    • Synchronous Channels Share the Same Counter
    • Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods
    • Synchronous Channels Supports Connection of one DMA Controller Channel Which Offers Buffer Transfer Without Processor Intervention To Update Duty-Cycle Registers
  • 2 Independent Events Lines Intended to Synchronize ADC Conversions
    • Programmable delay for Events Lines to delay ADC measurements
  • 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines DMA Controller Transfer Requests
  • 8 Programmable Fault Inputs Providing an Asynchronous Protection of PWM Outputs
    • 3 User Driven through PIO Inputs
    • PMC Driven when Crystal Oscillator Clock Fails
    • ADC Controller Driven through Configurable Comparison Function
    • Analog Comparator Controller Driven
    • Timer/Counter Driven through Configurable Comparison Function
  • Register Write Protection