14.1 Peripheral Identifiers
The following table defines the peripheral identifiers of the SAM E70/S70/V70/V71 devices. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller.
| Instance ID | Instance Name | NVIC Interrupt | PMC Clock Control | Description |
|---|---|---|---|---|
| 0 | SUPC | X | – | Supply Controller |
| 1 | RSTC | X | – | Reset Controller |
| 2 | RTC | X | – | Real Time Clock |
| 3 | RTT | X | – | Real Time Timer |
| 4 | WDT | X | – | Watchdog Timer |
| 5 | PMC | X | – | Power Management Controller |
| 6 | EFC | X | – | Enhanced Embedded Flash Controller |
| 7 | UART0 | X | X | Universal Asynchronous Receiver/Transmitter |
| 8 | UART1 | X | X | Universal Asynchronous Receiver/Transmitter |
| 9 | SMC | – | X | Static Memory Controller |
| 10 | PIOA | X | X | Parallel I/O Controller A |
| 11 | PIOB | X | X | Parallel I/O Controller B |
| 12 | PIOC | X | X | Parallel I/O Controller C |
| 13 | USART0 | X | X | Universal Synchronous/Asynchronous Receiver/Transmitter |
| 14 | USART1 | X | X | Universal Synchronous/Asynchronous Receiver/Transmitter |
| 15 | USART2 | X | X | Universal Synchronous/Asynchronous Receiver/Transmitter |
| 16 | PIOD | X | X | Parallel I/O Controller D |
| 17 | PIOE | X | X | Parallel I/O Controller E |
| 18 | HSMCI | X | X | Multimedia Card Interface |
| 19 | TWIHS0 | X | X | Two-wire Interface (I2C-compatible) |
| 20 | TWIHS1 | X | X | Two-wire Interface (I2C-compatible) |
| 21 | SPI0 | X | X | Serial Peripheral Interface |
| 22 | SSC | X | X | Synchronous Serial Controller |
| 23 | TC0_CHANNEL0 | X | X | 16-bit Timer Counter 0, Channel 0 |
| 24 | TC0_CHANNEL1 | X | X | 16-bit Timer Counter 0, Channel 1 |
| 25 | TC0_CHANNEL2 | X | X | 16-bit Timer Counter 0, Channel 2 |
| 26 | TC1_CHANNEL0 | X | X | 16-bit Timer Counter 1, Channel 0 |
| 27 | TC1_CHANNEL1 | X | X | 16-bit Timer Counter 1, Channel 1 |
| 28 | TC1_CHANNEL2 | X | X | 16-bit Timer Counter 1, Channel 2 |
| 29 | AFEC0 | X | X | Analog Front-End Controller |
| 30 | DACC | X | X | Digital-to-Analog Converter |
| 31 | PWM0 | X | X | Pulse-Width Modulation Controller |
| 32 | ICM | X | X | Integrity Check Monitor |
| 33 | ACC | X | X | Analog Comparator Controller |
| 34 | USBHS | X | X | USB Host/Device Controller |
| 35 | MCAN0 | X | X | CAN IRQ Line 0 |
| 36 | MCAN0 | INT1 | – | CAN IRQ Line 1 |
| 37 | MCAN1 | X | X | CAN IRQ Line 0 |
| 38 | MCAN1 | INT1 | – | CAN IRQ Line 1 |
| 39 | GMAC | X | X | Ethernet MAC |
| 40 | AFEC1 | X | X | Analog Front End Controller |
| 41 | TWIHS2 | X | X | Two-wire Interface |
| 42 | SPI1 | X | X | Serial Peripheral Interface |
| 43 | QSPI | X | X | Quad I/O Serial Peripheral Interface |
| 44 | UART2 | X | X | Universal Asynchronous Receiver/Transmitter |
| 45 | UART3 | X | X | Universal Asynchronous Receiver/Transmitter |
| 46 | UART4 | X | X | Universal Asynchronous Receiver/Transmitter |
| 47 | TC2_CHANNEL0 | X | X | 16-bit Timer Counter 2, Channel 0 |
| 48 | TC2_CHANNEL1 | X | X | 16-bit Timer Counter 2, Channel 1 |
| 49 | TC2_CHANNEL2 | X | X | 16-bit Timer Counter 2, Channel 2 |
| 50 | TC3_CHANNEL0 | X | X | 16-bit Timer Counter 3, Channel 0 |
| 51 | TC3_CHANNEL1 | X | X | 16-bit Timer Counter 3, Channel 1 |
| 52 | TC3_CHANNEL2 | X | X | 16-bit Timer Counter 3, Channel 2 |
| 53 | MLB | X | X | MediaLB IRQ 0 |
| 54 | MLB | X | – | MediaLB IRQ 1 |
| 55 | – | X | – | Reserved |
| 56 | AES | X | X | Advanced Encryption Standard |
| 57 | TRNG | X | X | True Random Number Generator |
| 58 | XDMAC | X | X | DMA Controller |
| 59 | ISI | X | X | Image Sensor Interface |
| 60 | PWM1 | X | X | Pulse-Width Modulation Controller |
| 61 | ARM | FPU | – | Arm Floating Point Unit interrupt associated with OFC, UFC, IOC, DZC and IDC bits. |
| 62 | Reserved | – | – | – |
| 63 | RSWDT | X | – | Reinforced Safety Watchdog Timer |
| 64 | ARM | CCW | – | Arm Cache ECC Warning |
| 65 | ARM | CCF | – | Arm Cache ECC Fault |
| 66 | GMAC | Q1 | – | GMAC Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1. |
| 67 | GMAC | Q2 | – | GMAC Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2. |
| 68 | ARM | IXC | – | Floating Point Unit Interrupt IXC associated with FPU cumulative exception bit. |
| 69 | I2SC0 | X | X | Inter-IC Sound Controller |
| 70 | I2SC1 | X | X | Inter-IC Sound Controller |
| 71 | GMAC | Q3 | – | GMAC Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3 |
| 72 | GMAC | Q4 | – | GMAC Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4 |
| 73 | GMAC | Q5 | – | GMAC Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5 |
