34.15 Asynchronous Page Mode
The SMC supports asynchronous burst reads in Page mode, provided that the Page mode is enabled (SMC_MODE.PMEN =1). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in the following table.
With Page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa) as shown in Page Mode Read Protocol. When in Page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page.
| Page Size | Page Address (see Note) | Data Address in the Page |
|---|---|---|
| 4 bytes | A[23:2] | A[1:0] |
| 8 bytes | A[23:3] | A[2:0] |
| 16 bytes | A[23:4] | A[3:0] |
| 32 bytes | A[23:5] | A[4:0] |