38.6.1.1 Power-On and Reset

The following figure describes the USBHS general states.

After a hardware reset, the USBHS is in Reset state. In this state:

• The USBHS is disabled. The USBHS Enable bit in the General Control register (USBHS_CTRL.USBE) is zero.
• The USBHS clock is stopped in order to minimize power consumption. The Freeze USB Clock bit (USBHS_CTRL.FRZCLK) is set.
• The UTMI is in Suspend mode.
• The internal states and registers of the Device and Host modes are reset.
• The DPRAM is not cleared and is accessible.

After writing a one to USBHS_CTRL.USBE, the USBHS enters the Device or the Host mode in idle state.

The USBHS can be disabled at any time by writing a zero to USBHS_CTRL.USBE. This acts as a hardware reset, except that the USBHS_CTRL.FRZCLK, USBHS_CTRL.UIMOD and USBHS_DEVCTRL.LS bits are not reset.