49.3 Block Diagram

Table 49-1. Timer Counter Clock Assignment
NameDefinition
TIMER_CLOCK1PCK6 or PCK7 (TC0.Ch0 only)
TIMER_CLOCK2MCK/8
TIMER_CLOCK3MCK/32
TIMER_CLOCK4MCK/128
TIMER_CLOCK5 (1) SLCK
  1. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Host Clock register), SLCK input is equivalent to Peripheral Clock.
  2. The PCK6 or PCK7 (TC0.Ch0 only) frequency must be at least three times lower than peripheral clock frequency.
Figure 49-1. Timer Counter Module N Block Diagram (N = 0,1,2,3)
Note:

The QDEC connections are detailed in Predefined Connection of the Quadrature Decoder with Timer Counters.

Table 49-2. Channel Signal Description
Signal NameDescription
XC0, XC1, XC2External Clock Inputs
TIOAxCapture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
TIOBxCapture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INTInterrupt Signal Output (internal signal)
SYNCSynchronization Input Signal (from configuration register)