27.6.11 RTC Interrupt Mask Register
| Name: | RTC_IMR |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TDERR | CAL | TIM | SEC | ALR | ACK | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – TDERR Time and/or Date Error Mask
| Value | Description |
|---|---|
| 0 |
The time and/or date error event is disabled. |
| 1 |
The time and/or date error event is enabled. |
Bit 4 – CAL Calendar Event Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The selected calendar event interrupt is disabled. |
| 1 |
The selected calendar event interrupt is enabled. |
Bit 3 – TIM Time Event Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The selected time event interrupt is disabled. |
| 1 |
The selected time event interrupt is enabled. |
Bit 2 – SEC Second Event Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The second periodic interrupt is disabled. |
| 1 |
The second periodic interrupt is enabled. |
Bit 1 – ALR Alarm Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The alarm interrupt is disabled. |
| 1 |
The alarm interrupt is enabled. |
Bit 0 – ACK Acknowledge Update Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The acknowledge for update interrupt is disabled. |
| 1 |
The acknowledge for update interrupt is enabled. |