33.4 I/O Lines Description

Table 33-1. EBI I/O Lines Description
Name Function Type Active Level
EBI
D0–D15 Data Bus I/O
A0–A23 Address Bus Output
NWAIT External Wait Signal Input Low
SMC
NCS0–EBI_NCS3 Chip Select Lines Output Low
NWR0–NWR1 Write Signals Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0–NBS1 Byte Mask Signals Output Low
EBI for NAND Flash Support
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low

The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment.

The following table details the connections between the SMC Memory Controller and the EBI pins.

Table 33-2. EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins SMC I/O Lines
NWR1/NBS1 NWR1
A0/NBS0 SMC_A0
A1 SMC_A1
A[11:2] SMC_A[11:2]
A12 SMC_A12
A[15:13] SMC_A[15:13]
A[25:16] SMC_A[25:16]
D[15:0] D[15:0]