46.6 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	UART_CR	7:0	TXDIS	TXEN	RXDIS	RXEN	RSTTX	RSTRX
		15:8				REQCLR				RSTSTA
		23:16
		31:24
0x04	UART_MR	7:0				FILTER
		15:8	CHMODE[1:0]			BRSRCCK	PAR[2:0]
		23:16
		31:24
0x08	UART_IER	7:0	PARE	FRAME	OVRE				TXRDY	RXRDY
		15:8	CMP						TXEMPTY
		23:16
		31:24
0x0C	UART_IDR	7:0	PARE	FRAME	OVRE				TXRDY	RXRDY
		15:8	CMP						TXEMPTY
		23:16
		31:24
0x10	UART_IMR	7:0	PARE	FRAME	OVRE				TXRDY	RXRDY
		15:8	CMP						TXEMPTY
		23:16
		31:24
0x14	UART_SR	7:0	PARE	FRAME	OVRE				TXRDY	RXRDY
		15:8	CMP						TXEMPTY
		23:16
		31:24
0x18	UART_RHR	7:0	RXCHR[7:0]
		15:8
		23:16
		31:24
0x1C	UART_THR	7:0	TXCHR[7:0]
		15:8
		23:16
		31:24
0x20	UART_BRGR	7:0	CD[7:0]
		15:8	CD[15:8]
		23:16
		31:24
0x24	UART_CMPR	7:0	VAL1[7:0]
		15:8		CMPPAR		CMPMODE
		23:16	VAL2[7:0]
		31:24
0x28 ... 0xE3	Reserved
0xE4	UART_WPMR	7:0								WPEN
		15:8	WPKEY[7:0]
		23:16	WPKEY[15:8]
		31:24	WPKEY[23:16]