22.4.1 Embedded Flash Organization
The embedded Flash interfaces with the internal bus. The embedded Flash is composed of the following:
- One memory plane organized in several pages of the same size for the code.
- A separate 2 x 512-byte memory area which includes the unique chip identifier.
- A separate 512-byte memory area for the user signature.
- Two 128-bit read buffers used for code read optimization.
- One 128-bit read buffer used for data read optimization.
- One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the entire flash address space, so that each word can be written to its final address.
- Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane.
- Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile memory bits (GPNVM bits).
The embedded Flash size, page size, organization of lock regions, and definition of GPNVM bits are specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command has been issued by the application, refer to the “Get Flash Descriptor Command”.
