15.1 Arm Cortex-M7 Configuration
The following table provides the configuration for the Arm Cortex-M7 processor in SAM E70/S70/V70/V71 devices.
| Features | Configuration |
|---|---|
| Debug | |
| Comparator set | Full comparator set: 4 DWT and 8 FPB comparators |
| ETM support | Instruction ETM interface |
| Internal Trace support (ITM) | ITM and DWT trace functionality implemented |
| CTI and WIC | Not embedded |
| TCM | |
| ITCM max size | 128 KB |
| DTCM max size | 256 KB |
| Cache | |
| Cache size | 16 KB for instruction cache, 16 KB for data cache |
| Number of sets | 256 for instruction cache, 128 for data cache |
| Number of ways | 2 for instruction cache, 4 for data cache |
| Number of words per cache line | 8 words (32 bytes) |
| ECC on Cache | Embedded |
| NVIC | |
| IRQ number | 74 |
| IRQ priority levels | 8 |
| MPU | |
| Number of regions | 16 |
| FPU | |
| FPU precision | Single and double precision |
| AHB Port | |
| AHBP addressing size | 512 MB |