15.1 Arm Cortex-M7 Configuration

The following table provides the configuration for the Arm Cortex-M7 processor in SAM E70/S70/V70/V71 devices.

Table 15-1. Arm Cortex-M7 Configuration
FeaturesConfiguration
Debug
Comparator setFull comparator set: 4 DWT and 8 FPB comparators
ETM supportInstruction ETM interface
Internal Trace support (ITM)ITM and DWT trace functionality implemented
CTI and WICNot embedded
TCM
ITCM max size128 KB
DTCM max size256 KB
Cache
Cache size16 KB for instruction cache, 16 KB for data cache
Number of sets256 for instruction cache, 128 for data cache
Number of ways2 for instruction cache, 4 for data cache
Number of words per cache line8 words (32 bytes)
ECC on CacheEmbedded
NVIC
IRQ number74
IRQ priority levels8
MPU
Number of regions16
FPU
FPU precisionSingle and double precision
AHB Port
AHBP addressing size512 MB