59.1.2 Supplying the Device With Two Separate Supplies

CAUTION: The board design must comply with power-up and power-down sequence guidelines provided in the “Power Considerations” chapter.
Power Supplies Schematic Example With Separate Power Supplies 59.3 Boot Program Hardware Constraints

Component values are given only as a typical example.

Note:

Note: Restrictions
With main supply < 3.0 V, USB is not usable.
With main supply < 2.0 V, AFE, DAC and Analog comparator are not usable.
With main supply and VDDIN > 3.0 V, all peripherals are usable.
Signal Name Recommended Pin Connection Description
VDDIN Decoupling/filtering capacitors

(100 nF and 4.7 μF) (1, 2)

Powers the voltage regulator, AFE, DAC, and Analog comparator power supply

Supply ripple must not exceed 20 mVrms for 10 kHz to
20 MHz range.

Warning: VDDIN and VDDIO must have the same level and must always be higher than VDDCORE.
Warning: Power up and power down sequences given in the “Power Considerations” chapter must be respected.
VDDIO Decoupling/filtering capacitors

(100 nF) (1, 2)

Powers the Peripheral I/O lines (Input/Output Buffers), backup part, 1 Kbytes of Backup SRAM, 32 kHz crystal oscillator, oscillator pads

Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop.

Supply ripple must not exceed 30 mVrms for 10 kHz to
10 MHz range.

Warning: VDDIN and VDDIO must have the same level and must always be higher than VDDCORE.
Warning: Powerup and powerdown sequences given in the “Power Considerations” chapter must be respected.
VDDUTMII Decoupling capacitor (100 nF) (1) (2) Powers the USB transceiver interface. Must be connected to VDDIO.

For USB operations, VDDUTMII and VDDIO voltage ranges must be from 3.0V to 3.6V.

Must always be connected even if the USB is not used.

Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop.

Supply ripple must not exceed 20 mVrms for 10 kHz to 10 MHz range.
VDDPLLUSB Decoupling/filtering RLC circuit (1) Powers the UTMI PLL and the 3 to 20 MHz oscillator.

For USB operations, VDDPLLUSB should be between 3.0V and 3.6V.

The VDDPLLUSB power supply pin draws small current, but it is noise sensitive. Care must be taken in VDDPLLUSB power supply routing, decoupling and also on bypass capacitors.

Supply ripple must not exceed 10 mVrms for 10 kHz to
10 MHz range.
VDDOUT Left unconnected Voltage Regulator Output
VDDCORE Decoupling capacitor (100 nF) (1) (2) Powers the core, embedded memories and peripherals.

Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop.

Supply ripple must not exceed 20 mVrms for 10 kHz to
20 MHz range.

Warning: Powerup and powerdown sequences given in the “Power Considerations” chapter must be respected.
VDDPLL Decoupling/filtering capacitors ferrite beads

(100 nF and 470 Ohm @ 100 MHz) (1) (2)

 Powers the PLLA and the fast RC oscillator.

The VDDPLL power supply pin draws small current, but it is noise sensitive. Care must be taken in VDDPLL power supply routing, decoupling and also on bypass capacitors.

Supply ripple must not exceed 20 mVrms for 10 kHz to 10 MHz range and 10 mVrms for higher frequencies.
VDDUTMIC Decoupling/filtering capacitors ferrite beads

(100 nF and 470 Ohm @ 100 MHz) (1) (2)

 Powers the USB transceiver core.

Must always be connected even if the USB is not used.

Decoupling/filtering capacitors/ferrite beads must be added to improve startup stability and reduce source voltage drop.

Supply ripple must not exceed 10 mVrms for 10 kHz to
10 MHz range.
GND Voltage Regulator, Core Chip and Peripheral I/O lines ground GND pins are common to VDDIN, VDDCORE and VDDIO pins.

GND pins should be connected as shortly as possible to the system ground plane.
GNDUTMI UDPHS and UHPHS UTMI+ Core and interface ground GNDUTMI pins are common to VDDUTMII and VDDUTMIC pins.

GNDUTMI pins should be connected as shortly as possible to the system ground plane.
GNDPLL PLLA cell and Main Oscillator ground GNDPLL pin is provided for VDDPLL pin. GNDPLL pin should be connected as shortly as possible to the system ground plane.
GNDANA Analog ground GNDANA pins are common to AFE, DAC and ACC supplied by VDDIN pin.

GNDANA pins should be connected as shortly as possible to the system ground plane.
GNDPLLUSB USB PLL ground GNDPLLUSB pin is provided for VDDPLLUSB pin. GNDPLLUSB pin should be connected as shortly as possible to the system ground plane.
Note:
  1. These values are given only as a typical example.
  2. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin, vias should be avoided.