Programmable transfer delays between
consecutive transfers, between clock and data, between deactivation and activation
of chip select
Interface to serial peripherals such as ADCs, DACs, LCD
controllers, CAN controllers and sensors
8-bit/16-bit programmable data length
Serial Memory Mode
Interface to serial Flash memories operating in Single-bit SPI, Dual SPI and Quad SPI
Interface to serial Flash Memories
operating in Single Data Rate or Double Data Rate Modes
Supports “Execute In Place” (XIP)— code execution by the system directly from a serial Flash memory
Flexible instruction register for compatibility with all serial Flash memories
32-bit address mode (default is 24-bit address) to support serial Flash memories larger than 128 Mbits
Continuous read mode
Scrambling/unscrambling “On-The-Fly”
Connection to DMA Channel Capabilities Optimizes Data Transfers
One channel for the receiver, one channel for the transmitter
Register Write Protection
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
