57.13.1.6.2 SPI Timings

Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.

Table 57-44. SPI Timings
SymbolParameterConditionsMinMaxUnit
SPI0MISO Setup time before SPCK rises (Host)3.3V domain12.4–ns
SPI1MISO Hold time after SPCK rises (Host)3.3V domain0–ns
SPI2SPCK rising to MOSI Delay (Host)3.3V domain-3.72.2ns
SPI3MISO Setup time before SPCK falls (Host)3.3V domain12.6–ns
SPI4MISO Hold time after SPCK falls (Host)3.3V domain0–ns
SPI5SPCK falling to MOSI Delay (Host)3.3V domain-3.62.0ns
SPI6SPCK falling to MISO Delay (Client)3.3V domain3.011.9ns
SPI7MOSI Setup time before SPCK rises (Client)3.3V domain1.2–ns
SPI8MOSI Hold time after SPCK rises (Client)3.3V domain0.6–ns
SPI9SPCK rising to MISO Delay (Client)3.3V domain3.012.0ns
SPI10MOSI Setup time before SPCK falls (Client)3.3V domain1.2–ns
SPI11MOSI Hold time after SPCK falls (Client)3.3V domain0.6–ns
SPI12NPCS setup to SPCK rising (Client)3.3V domain3.9–ns
SPI13NPCS hold after SPCK falling (Client)3.3V domain0–ns
SPI14NPCS setup to SPCK falling (Client)3.3V domain4.0–ns
SPI15NPCS hold after SPCK falling (Client)3.3V domain0–ns

Note that in SPI Host mode, the device does not sample the data (MISO) on the opposite edge where the data clocks out (MOSI), but the same edge is used. See Figure 57-13 and Figure 57-14.