4.4 AC Characteristics
| Parameter | Symbol | Minimum | Maximum | Units | Test Conditions |
|---|---|---|---|---|---|
| Clock Frequency, SK | fSK | 0 | 2 | MHz | 4.5V ≤ VCC ≤ 5.5V |
| 0 | 1 | MHz | 2.5V ≤ VCC ≤ 5.5V | ||
| 0 | 250 | kHz | 1.7V ≤ VCC ≤ 5.5V | ||
| High Time, SK | tSKH | 250 | — | ns | 2.5V ≤ VCC ≤ 5.5V |
| 1000 | — | ns | 1.7V ≤ VCC ≤ 5.5V | ||
| Low Time, SK | tSKL | 250 | — | ns | 2.5V ≤ VCC ≤ 5.5V |
| 1000 | — | ns | 1.7V ≤ VCC ≤ 5.5V | ||
| Minimum CS Low Time | tCS | 250 | — | ns | 2.5V ≤ VCC ≤ 5.5V |
| 1000 | — | ns | 1.7V ≤ VCC ≤ 5.5V | ||
| CS Setup Time | tCSS | 50 | — | ns | 2.5V ≤ VCC ≤ 5.5V, Relative to SK |
| 200 | — | ns | 1.7V ≤ VCC ≤ 5.5V, Relative to SK | ||
| DI Setup Time | tDIS | 100 | — | ns | 2.5V ≤ VCC ≤ 5.5V, Relative to SK |
| 400 | — | ns | 1.7V ≤ VCC ≤ 5.5V, Relative to SK | ||
| CS Hold Time | tCSH | 0 | — | ns | Relative to SK |
| DI Hold Time | tDIH | 100 | — | ns | 2.5V ≤ VCC ≤ 5.5V, Relative to SK |
| 400 | — | ns | 1.7V ≤ VCC ≤ 5.5V, Relative to SK | ||
| Output Delay to 1 | tPD1 | — | 250 | ns | 2.5V ≤ VCC ≤ 5.5V |
| — | 1000 | ns | 1.7V ≤ VCC ≤ 5.5V | ||
| Output Delay to 0 | tPD0 | — | 250 | ns | 2.5V ≤ VCC ≤ 5.5V |
| — | 1000 | ns | 1.7V ≤ VCC ≤ 5.5V | ||
| CS to Status Valid | tSV | — | 250 | ns | 2.5V ≤ VCC ≤ 5.5V |
| — | 1000 | ns | 1.7V ≤ VCC ≤ 5.5V, | ||
| CS to DO in High‑impedance | tDF | — | 150 | ns | 2.5V ≤ VCC ≤ 5.5V, CS = VIL |
| — | 400 | ns | 1.7V ≤ VCC ≤ 5.5V, CS = VIL | ||
| Write Cycle Time | tWP | 0.1 | 5 | ms | 1.7V ≤ VCC ≤ 5.5V |
Note:
- Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
