2 Pin Descriptions
The descriptions of the pins are listed below in the Table 2-1.
| Name | 8‑Lead SOIC | 8‑Lead TSSOP | 8‑Pad UDFN(1) | 8-Ball VFBGA | Function |
|---|---|---|---|---|---|
| CS | 1 | 1 | 1 | 1 | Chip Select |
| SK | 2 | 2 | 2 | 2 | Serial Data Clock |
| DI | 3 | 3 | 3 | 3 | Serial Data Input |
| DO | 4 | 4 | 4 | 4 | Serial Data Output |
| GND | 5 | 5 | 5 | 5 | Ground |
| ORG | 6 | 6 | 6 | 6 | Internal Organization |
| NC | 7 | 7 | 7 | 7 | No Connect |
| VCC | 8 | 8 | 8 | 8 | Device Power Supply |
Note:
- The exposed pad on this package can be connected to GND or left floating.