5 Device Commands and Addressing

The AT93C56B/AT93C66B is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of CS and consists of a Start bit (SB), followed by the appropriate opcode and the desired memory address location.

Table 5-1. AT93C56B/AT93C66B Instruction Set
Instruction	SB	Opcode	Address		Data		Comments
Instruction	SB	Opcode	X8⁽¹⁾	X16⁽¹⁾	X8	X16	Comments
`READ`	`1`	`10`	A₈‑A₀	A₇‑A₀			Reads data stored in memory at specified address.
`EWEN`	`1`	`00`	11XXXXXXX	11XXXXXX			Write Enable must precede all programming modes.
`ERASE`	`1`	`11`	A₈‑A₀	A₇‑A₀			Erases memory location A_N‑A₀.
`WRITE`	`1`	`01`	A₈‑A₀	A₇‑A₀	D₇‑D₀	D₁₅‑D₀	Writes memory location A_N‑A₀.
`ERAL`	`1`	`00`	10XXXXXXX	10XXXXXX			Erases all memory locations. Valid only at V_CC3. See Table 4-2.
`WRAL`	`1`	`00`	01XXXXXXX	01XXXXXX	D₇‑D₀	D₁₅‑D₀	Writes all memory locations. Valid only at V_CC3. See Table 4-2.
`EWDS`	`1`	`00`	00XXXXXXX	00XXXXXX			Disables all programming instructions.

Note:

The ‘X’ in the address field represents a “don’t care” bit and must be sent to the device.

Table 5-2. Organization Key for Timing Diagrams
I/O	AT93C56B (2 Kbits)		AT93C66B (4 Kbits)
I/O	x8	x16	x8	x16
A_N	A₈⁽¹⁾	A₇⁽²⁾	A₈	A₇
D_N	D₇	D₁₅	D₇	D₁₅

Note:

A₈ is a “don’t care” value, but the extra clock is required.
A₇ is a “don’t care” value, but the extra clock is required.