14.1.1 Hardware Implementation of Sinc3 Filter
(Ask a Question)The following figure shows the hardware implementation of Sinc3 Filter.
The clk_adc_i signal is the modulator clock from the ADC to the Sinc3 Filter. The filter implements three sequential integrations at the rate of clk_adc_i. A decimated clock is generated internally based on configuration parameters as shown in the following equation. The output of the third integrator is differentiated serially three times with respect to the decimated clock to generate the output.
The equivalent resolution of the Sinc3 Filter output with respect to decimation factor is represented by the following equation.
