2.4.1 Simulation

The following steps describe how to simulate the core using the testbench:

  1. Open the Libero SoC application, click Libero SoC Catalog tab, expand Solutions-MotorControl,
  2. In the Catalog dialog box, double-click BLDC Estimator, and then click OK. The documentation associated with the IP are listed under Documentation.
    Important: If you do not see the Catalog tab, navigate to View Windows menu and click Catalog to make it visible.
    Figure 2-4. BLDC Estimator IP Core in Libero SoC Catalog
  3. On the Stimulus Hierarchy tab, right-click testbench (bldc_estimator_tb.v), point to Simulate Pre-Synth Design, and then click Open Interactively.
    Important: If you do not see the Stimulus Hierarchy tab, navigate to View > Windows menu and click Stimulus Hierarchy to make it visible.
    Figure 2-5. Simulating Pre-Synthesis Design

    ModelSim opens with the testbench file, as shown in the following figure.

    Figure 2-6. ModelSim Simulation Window
Important: If the simulation is interrupted due to the runtime limit specified in the .do file, use the run -all command to complete the simulation.