2 Device Utilization and Performance

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The following table lists the device utilization used for BLDC Estimator.

Table 2-2. BLDC Estimator Utilization
Device Details		Resources			Performance (MHz)	RAMs		Math Blocks	Chip Globals
Family	Device	LUTs	DFF		Performance (MHz)	LSRAM	μSRAM	Math Blocks	Chip Globals
PolarFire® SoC	MPFS250T	1409	876		200	0	0	3	0
PolarFire	MPF300T	1373	876		200	0	0	3	0
SmartFusion® 2	M2S150	1473	883		170	0	0	3	0

Important:

The data in this table is captured using typical synthesis and layout settings. CDR reference clock source was set to Dedicated with other configurator values unchanged.
Clock is constrained to 200 MHz while running the timing analysis to achieve the performance numbers.

Rev: A