11.4.1 Simulation

The following steps describe how to simulate the core using the testbench:

Open Libero SoC, click Catalog tab, and click Solutions-MotorControl.
Double-click Rate Limiter, and then click OK. The documentation associated with the IP are listed under Documentation.
Important: If you do not see the Catalog tab, click View, open Windows menu, and then click Catalog to make it visible.
Figure 11-6. Rate Limiter IP Core in Libero SoC Catalog
On the Stimulus Hierarchy tab, click the testbench (rate_limiter_tb.v), point to Simulate Pre-Synth Design, and then click Open Interactively.
Important: If you do not see the Stimulus Hierarchy tab, click View, open Windows menu, and then click Stimulus Hierarchy to make it visible.
Figure 11-7. Simulating Pre-Synthesis Design

ModelSim opens with the testbench file, as shown in the following figure.
Figure 11-8. ModelSim Simulation Window

Important: If the simulation is interrupted due to the runtime limit specified in the .do file, use the

run
                -all

command to complete the simulation.