11.2.1 Inputs and Outputs Signals
(Ask a Question)The following table lists the input and output ports of Rate Limiter.
| Signal Name | Direction | Description |
|---|---|---|
| reset_i | Input | Asynchronous active low reset signal to design |
| sys_clk_i | Input | System clock |
| start_i | Input | Start signal for module computation - high for one system clock cycle |
| soft_stop_i | Input | Triggers Soft Stop |
| reset_rl_i | Input | Resets the Rate Limiter output immediately |
| rl_in_i | Input | Input reference |
| slew_count_i | Input | Number of start signals after which the output is updated |
| rate_count_i | Input | Rate at which the output is incremented or decremented |
| direction_i | Input | Refers to the motor direction |
| rl_out_o | Output | Rate limited output of the block |
| rl_done_o | Output | Completion of block execution - high for one system clock cycle |