18.2.1 Inputs and Outputs Signals
(Ask a Question)The following table lists the input and output ports of Three-phase PWM.
| Signal Name | Direction | Description |
|---|---|---|
| reset_i | Input | Asynchronous active low reset signal |
| sys_clk_i | Input | System Clock |
| en_pwm_i | Input |
Asynchronous enables: When set to 0, PWM outputs are driven to 0 When set to 1, PWM outputs are generated. |
| en_dual_trig_i | Input |
When set to 1, PWM produces two trigger pulses distributed evenly per cycle at the midmatch_o output. When set to 0, PWM produces one trigger pulse per cycle at the midmatch_o output. |
| va_i | Input | Phase A duty cycle with respect to pwm_period |
| vb_i | Input | Phase B duty cycle with respect to pwm_period |
| vc_i | Input | Phase C duty cycle with respect to pwm_period |
| pwm_period_i | Input | Time period of PWM in number of system clock time |
| dead_time_i | Input | Dead time |
| delay_time_i | Input | Delay time |
| midmatch_o | Output |
Period mid-match interrupt produces two pulses per PWM cycle when en_dual_trig_i input is 1, and produces one pulse per PWM cycle when en_dual_trig_i input is 0. |
| PWM_AH_O | Output | Channel A PWM for high side switch |
| PWM_AL_O | Output | Channel A PWM for low side switch |
| PWM_BH_O | Output | Channel B PWM for high side switch |
| PWM_BL_O | Output | Channel B PWM for low side switch |
| PWM_CH_O | Output | Channel C PWM for high side switch |
| PWM_CL_O | Output | Channel C PWM for low side switch |