34.20.1 UxCON0

UART Control Register 0
Note:
  1. Changing the UART MODE while ON = 1 may cause unexpected results.
  2. Clearing TXEN or RXEN will not clear the corresponding buffers. Use TXBE or RXBE to clear the buffers.
  3. ABDEN is read-only when MODE > ‘b0111.
  4. Full-featured UARTs only.
Name: UxCON0
Address: 0x1B9,0x1CD

Bit 76543210 
 BRGSABDENTXENRXENMODE[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – BRGS Baud Rate Generator Speed Select

ValueDescription
1 Baud Rate Generator is high speed with 4 baud clocks per bit
0 Baud Rate Generator is normal speed with 16 baud clocks per bit

Bit 6 – ABDEN  Auto-Baud Detect Enable(3)

ValueDescription
1 Auto-baud is enabled. Receiver is waiting for Sync character (0x55).
0 Auto-baud is not enabled or auto-baud is complete

Bit 5 – TXEN  Transmit Enable Control(2)

ValueDescription
1 Transmit is enabled. TX output pin drive is forced on when transmission is active and is controlled by PORT TRIS control when transmission is Idle.
0 Transmit is disabled. TX output pin drive is controlled by PORT TRIS control.

Bit 4 – RXEN  Receive Enable Control(2)

ValueDescription
1 Receiver is enabled
0 Receiver is disabled

Bits 3:0 – MODE[3:0]  UART Mode Select(1)

ValueDescription
1111 - 1101 Reserved
1100 LIN Host/Client mode(4)
1011 LIN Client Only mode(4)
1010 DMX mode(4)
1001 DALI Control Gear mode(4)
1000 DALI Control Device mode(4)
0111 - 0101 Reserved
0100 Asynchronous 9-bit UART Address mode. 9th bit: 1 = address, 0 = data
0011 Asynchronous 8-bit UART mode with 9th bit even parity
0010 Asynchronous 8-bit UART mode with 9th bit odd parity
0001 Asynchronous 7-bit UART mode
0000 Asynchronous 8-bit UART mode
Changing the UART MODE while ON = 1 may cause unexpected results. Clearing TXEN or RXEN will not clear the corresponding buffers. Use TXBE or RXBE to clear the buffers. ABDEN is read-only when MODE > ‘b0111. Full-featured UARTs only.