39.4 Maximum Clock Frequencies

Table 39-3. Maximum GCLK Generator Output Frequencies (Device Variant A)
Symbol	Description	Conditions	Max.	Units
f_GCLKGEN0 / f_{GCLK_MAIN} f_GCLKGEN1 f_GCLKGEN2 f_GCLKGEN3 f_GCLKGEN4 f_GCLKGEN5 f_GCLKGEN6 f_GCLKGEN7 f_GCLKGEN8	GCLK Generator Output Frequency	Undivided	96	MHz
	GCLK Generator Output Frequency	Divided	32	MHz

Table 39-4. Maximum Peripheral Clock Frequencies (Device Variant A)
Symbol	Description	Max.	Units
f_CPU	CPU clock frequency	32	MHz
f_AHB	AHB clock frequency	32	MHz
f_APBA	APBA clock frequency	32	MHz
f_APBB	APBB clock frequency	32	MHz
f_APBC	APBC clock frequency	32	MHz
f_{GCLK_DFLL48M_REF}	DFLL48M Reference clock frequency	33	KHz
f_{GCLK_DPLL}	FDPLL96M Reference clock frequency	2	MHz
f_{GCLK_DPLL_32K}	FDPLL96M 32k Reference clock frequency	32	KHz
f_{GCLK_WDT}	WDT input clock frequency	48	MHz
f_{GCLK_RTC}	RTC input clock frequency	48	MHz
f_{GCLK_EIC}	EIC input clock frequency	48	MHz
f_{GCLK_USB}	USB input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_0}	EVSYS channel 0 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_1}	EVSYS channel 1 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_2}	EVSYS channel 2 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_3}	EVSYS channel 3 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_4}	EVSYS channel 4 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_5}	EVSYS channel 5 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_6}	EVSYS channel 6 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_7}	EVSYS channel 7 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_8}	EVSYS channel 8 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_9}	EVSYS channel 9 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_10}	EVSYS channel 10 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_11}	EVSYS channel 11 input clock frequency	48	MHz
f_{GCLK_SERCOMx_SLOW}	Common SERCOM slow input clock frequency	48	MHz
f_{GCLK_SERCOM0_CORE}	SERCOM0 input clock frequency	48	MHz
f_{GCLK_SERCOM1_CORE}	SERCOM1 input clock frequency	48	MHz
f_{GCLK_SERCOM2_CORE}	SERCOM2 input clock frequency	48	MHz
f_{GCLK_SERCOM3_CORE}	SERCOM3 input clock frequency	48	MHz
f_{GCLK_SERCOM4_CORE}	SERCOM4 input clock frequency	48	MHz
f_{GCLK_SERCOM5_CORE}	SERCOM5 input clock frequency	48	MHz
f_{GCLK_TCC0}, f_{GCLK_TCC1}	TCC0, TCC1 input clock frequency	96	MHz
f_{GCLK_TCC2}, f_{GCLK_TC3}	TCC2, TC3 input clock frequency	96	MHz
f_{GCLK_TC4}, f_{GCLK_TC5}	TC4, TC5 input clock frequency	48	MHz
f_{GCLK_TC6}, f_{GCLK_TC7}	TC6, TC7 input clock frequency	48	MHz
f_{GCLK_ADC}	ADC input clock frequency	48	MHz
f_{GCLK_AC_DIG}	AC digital input clock frequency	48	MHz
f_{GCLK_AC_ANA}	AC analog input clock frequency	64	KHz
f_{GCLK_DAC}	DAC input clock frequency	48	MHz
f_{GCLK_PTC}	PTC input clock frequency	48	MHz
f_{GCLK_I2S_0}	I2S serializer 0 input clock frequency	13	MHz
f_{GCLK_I2S_1}	I2S serializer 1 input clock frequency	13	MHz

Table 39-5. Maximum GCLK Generator Output Frequencies (Device Variant B, C, D, and L)
Symbol	Description	Conditions	Max.	Units
f_GCLKGEN0 / f_{GCLK_MAIN} f_GCLKGEN1 f_GCLKGEN2 f_GCLKGEN3 f_GCLKGEN4 f_GCLKGEN5 f_GCLKGEN6 f_GCLKGEN7 f_GCLKGEN8	GCLK Generator Output Frequency	Undivided	96	MHz
	GCLK Generator Output Frequency	Divided	48	MHz

Table 39-6. Maximum Peripheral Clock Frequencies (Device Variant B, C, D, and L)
Symbol	Description	Max.	Units
f_CPU	CPU clock frequency	48	MHz
f_AHB	AHB clock frequency	48	MHz
f_APBA	APBA clock frequency	48	MHz
f_APBB	APBB clock frequency	48	MHz
f_APBC	APBC clock frequency	48	MHz
f_{GCLK_DFLL48M_REF}	DFLL48M Reference clock frequency	33	KHz
f_{GCLK_DPLL}	FDPLL96M Reference clock frequency	2	MHz
f_{GCLK_DPLL_32K}	FDPLL96M 32k Reference clock frequency	32	KHz
f_{GCLK_WDT}	WDT input clock frequency	48	MHz
f_{GCLK_RTC}	RTC input clock frequency	48	MHz
f_{GCLK_EIC}	EIC input clock frequency	48	MHz
f_{GCLK_USB}	USB input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_0}	EVSYS channel 0 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_1}	EVSYS channel 1 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_2}	EVSYS channel 2 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_3}	EVSYS channel 3 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_4}	EVSYS channel 4 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_5}	EVSYS channel 5 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_6}	EVSYS channel 6 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_7}	EVSYS channel 7 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_8}	EVSYS channel 8 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_9}	EVSYS channel 9 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_10}	EVSYS channel 10 input clock frequency	48	MHz
f_{GCLK_EVSYS_CHANNEL_11}	EVSYS channel 11 input clock frequency	48	MHz
f_{GCLK_SERCOMx_SLOW}	Common SERCOM slow input clock frequency	48	MHz
f_{GCLK_SERCOM0_CORE}	SERCOM0 input clock frequency	48	MHz
f_{GCLK_SERCOM1_CORE}	SERCOM1 input clock frequency	48	MHz
f_{GCLK_SERCOM2_CORE}	SERCOM2 input clock frequency	48	MHz
f_{GCLK_SERCOM3_CORE}	SERCOM3 input clock frequency	48	MHz
f_{GCLK_SERCOM4_CORE}	SERCOM4 input clock frequency	48	MHz
f_{GCLK_SERCOM5_CORE}	SERCOM5 input clock frequency	48	MHz
f_{GCLK_TCC0}, f_{GCLK_TCC1}	TCC0, TCC1 input clock frequency	96	MHz
f_{GCLK_TCC2}, f_{GCLK_TCC3}, f_{GCLK_TC3}	TCC2, TCC3,TC3 input clock frequency	96	MHz
f_{GCLK_TC4}, f_{GCLK_TC5}	TC4, TC5 input clock frequency	48	MHz
f_{GCLK_TC6}, f_{GCLK_TC7}	TC6, TC7 input clock frequency	48	MHz
f_{GCLK_ADC}	ADC input clock frequency	48	MHz
f_{GCLK_AC_DIG}	AC digital input clock frequency	48	MHz
f_{GCLK_AC_ANA}	AC analog input clock frequency	64	KHz
f_{GCLK_AC1_DIG}	AC1 digital input clock frequency	48	MHz
f_{GCLK_AC1_ANA}	AC1 analog input clock frequency	64	KHz
f_{GCLK_DAC}	DAC input clock frequency	48	MHz
f_{GCLK_PTC}	PTC input clock frequency	48	MHz
f_{GCLK_I2S_0}	I2S serializer 0 input clock frequency	13	MHz
f_{GCLK_I2S_1}	I2S serializer 1 input clock frequency	13	MHz

SAM D21/DA1 Family

39.4 Maximum Clock Frequencies